Sr Front End Design Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: We are seeking a seasoned Senior Design Lead / Manager with the right mix of technical and management skills to manage and lead a small team of talented design engineers. As an expert in building IP solutions around PCIe/CXL and Host DMA technologies, you have had significant success delivering IOP solutions of significant complexity. You are meticulous about Power, Performance and Area while driving schedule. As a member of the PCIe/CXL based solution design team, you will help bring to life cutting-edge designs, you will work closely with the architecture, Physical Design, and Design verification teams, and product engineers to achieve first pass silicon success. THE PERSON: You have excellent communication and presentation skills, demonstrated through presentations, trainings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. You have a passion for modern, complex microarchitecture, and digital design. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: You will work on next generation PCIe / CXL and connectivity solutions to enable a vast variety of applications. Some of the key responsibilities would be Microarchitecture development of IP subsystems Scoping, planning, and driving the front end design of complex IPs Resource management and planning for concurrent projects Manage and provide technical leadership and guidance to a small design team As needed, owning, coding, debugging aspects of the IP Work closely with verification (Debug, coverage, testplan), architecture (features), validation, physical design, security, dfx, power, and program management to deliver IPs on-time with high quality. Post-silicon support PREFERRED EXPERIENCE: Expertise in front end ASIC development flows and methodologies Knowledge of FPGA based IP development flows High performance, multi-queue DMA architecture and architecture experience IP integration Expertise in system verilog Expertise in AXI/AMBA protocol Knowledge of NoC subsytems Address translation Aperture protection Interleaving Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power. Verification - coverage, testplan, debug Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal) Ability to work and effectively collaborate with partners Experience with rtl simulation tools, rtl linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power, SEU tradeoffs), Experience with PCIe (AXI bridging, performance, ordering, MSIX, Virtual functions, error handling), CXL, Ethernet, DDR3/4/5, LPDDR3/4, HBM Knowledge of scripting languages like Perl, tcl or cshell Leadership/Management of small team of IP/SOC design engineers Strong communication, collaboration, and presentation skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. THE ROLE: We are seeking a seasoned Senior Design Lead / Manager with the right mix of technical and management skills to manage and lead a small team of talented design engineers. As an expert in building IP solutions around PCIe/CXL and Host DMA technologies, you have had significant success delivering IOP solutions of significant complexity. You are meticulous about Power, Performance and Area while driving schedule. As a member of the PCIe/CXL based solution design team, you will help bring to life cutting-edge designs, you will work closely with the architecture, Physical Design, and Design verification teams, and product engineers to achieve first pass silicon success. THE PERSON: You have excellent communication and presentation skills, demonstrated through presentations, trainings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. You have a passion for modern, complex microarchitecture, and digital design. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: You will work on next generation PCIe / CXL and connectivity solutions to enable a vast variety of applications. Some of the key responsibilities would be Microarchitecture development of IP subsystems Scoping, planning, and driving the front end design of complex IPs Resource management and planning for concurrent projects Manage and provide technical leadership and guidance to a small design team As needed, owning, coding, debugging aspects of the IP Work closely with verification (Debug, coverage, testplan), architecture (features), validation, physical design, security, dfx, power, and program management to deliver IPs on-time with high quality. Post-silicon support PREFERRED EXPERIENCE: Expertise in front end ASIC development flows and methodologies Knowledge of FPGA based IP development flows High performance, multi-queue DMA architecture and architecture experience IP integration Expertise in system verilog Expertise in AXI/AMBA protocol Knowledge of NoC subsytems Address translation Aperture protection Interleaving Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power. Verification - coverage, testplan, debug Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal) Ability to work and effectively collaborate with partners Experience with rtl simulation tools, rtl linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power, SEU tradeoffs), Experience with PCIe (AXI bridging, performance, ordering, MSIX, Virtual functions, error handling), CXL, Ethernet, DDR3/4/5, LPDDR3/4, HBM Knowledge of scripting languages like Perl, tcl or cshell Leadership/Management of small team of IP/SOC design engineers Strong communication, collaboration, and presentation skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Tags: No, USD $176,400.00/Yr., USD $252,000.00/Yr., US Careers (External)