Rivos
CPU Microarchitecture & Logic Design - Full time
Rivos, Austin, Texas, us, 78716
Positions are open for full-time in the areas of CPU microarchitecture and logic design, in the areas of memory management, load/store pipeline, cache, power management, debug features, and bus interface designs. We are looking for junior to mid-level of talent, from new college grads to about ten years of experience.
Responsibilities
Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerRequirements
Thorough knowledge of microprocessor architecture and microarchitecture in one or more of the following areas: memory management, load/store execution, cache and memory subsystems, bus interface, debug features, and power managementKnowledge of System VerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high performance techniques and trade-offs in a CPU microarchitectureExperience in C or C++ programmingExperience using an interpretive language such as Perl or PythonEducation and Experience
PhD, Master's Degree or Bachelor's Degree in technical subject area.
Responsibilities
Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerRequirements
Thorough knowledge of microprocessor architecture and microarchitecture in one or more of the following areas: memory management, load/store execution, cache and memory subsystems, bus interface, debug features, and power managementKnowledge of System VerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high performance techniques and trade-offs in a CPU microarchitectureExperience in C or C++ programmingExperience using an interpretive language such as Perl or PythonEducation and Experience
PhD, Master's Degree or Bachelor's Degree in technical subject area.