Eliyan
Physical Design Lead
Eliyan, San Francisco, California, United States, 94199
Join the leading chiplet startup! As the Eliyan Physical Design Engineer/Lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining, implementing, and ensuring correctness of 8GHz+ high speed blocks in 5/4/3/2nm processes. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.Key Responsibilities:
Leading a team of PD engineers developing chiplets and chiplet IPs.Define innovative and efficient design methodologies from architecture, uArch, functional verification, physical implementation, and post-Si bringup and productization.Work with cross functional teams across the company to deliver customer-ready products.Interview and attract strong engineers.Establish methodologies and flows for 8 GHz Synthesis and P&R, CTS, and custom routes.Integration of Analog/Mixed signal blocks, custom routes, and Power routing.Develop flows that yield designs that are correct by construction.Work with analog and digital designers to understand block design requirements.Automate flows and processes to maximize engineer efficiency.Develop flows for identifying weaknesses in implementations/PPA.Automate sign-off tools for timing, DFM, reliability, EM/IR.Minimum Qualifications:
Expertise in multiple areas of physical design, timing, and signoff.Strong scripting and automation skills.BS EE or equivalent, with 5 years of relevant experience.Ideal Qualifications:
Deep expertise in P&R, Static Timing, CTS, Synthesis, EM/IR, and DFM.Strong bias for innovations across all aspects of design leading to better product PPA and better schedule to revenue.Knowledge of PHYs, DRAM interfaces, a plus.Working knowledge of reliability mechanisms and methods to address those.Knowledge of UPF and power-aware designs.MS/PhD EE or equivalent, with 7+ years of experience.
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Leading a team of PD engineers developing chiplets and chiplet IPs.Define innovative and efficient design methodologies from architecture, uArch, functional verification, physical implementation, and post-Si bringup and productization.Work with cross functional teams across the company to deliver customer-ready products.Interview and attract strong engineers.Establish methodologies and flows for 8 GHz Synthesis and P&R, CTS, and custom routes.Integration of Analog/Mixed signal blocks, custom routes, and Power routing.Develop flows that yield designs that are correct by construction.Work with analog and digital designers to understand block design requirements.Automate flows and processes to maximize engineer efficiency.Develop flows for identifying weaknesses in implementations/PPA.Automate sign-off tools for timing, DFM, reliability, EM/IR.Minimum Qualifications:
Expertise in multiple areas of physical design, timing, and signoff.Strong scripting and automation skills.BS EE or equivalent, with 5 years of relevant experience.Ideal Qualifications:
Deep expertise in P&R, Static Timing, CTS, Synthesis, EM/IR, and DFM.Strong bias for innovations across all aspects of design leading to better product PPA and better schedule to revenue.Knowledge of PHYs, DRAM interfaces, a plus.Working knowledge of reliability mechanisms and methods to address those.Knowledge of UPF and power-aware designs.MS/PhD EE or equivalent, with 7+ years of experience.
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