Micron Technology, Inc.
DRAM Design Rule - Director - TPG
Micron Technology, Inc., Boise, Idaho, United States, 83708
Micron Technology, Inc. DRAM Design Rule - Director - TPG Boise, Idaho
Our vision is to transform how the world uses information to enrich life for
all
.
Check all associated application documentation thoroughly before clicking on the apply button at the bottom of this description.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.Micron has a unique opportunity for a highly experienced DRAM Design Rule Engineer to join our leadership team. As Director - DRAM Design Rule Enablement team, your primary leadership responsibility is to be a catalyst to next-generation DRAM development efforts! We exercise deep knowledge on defining, executing, and coordinating effective actions to enable the project to hit key achievements and timelines.Responsibilities include but are not limited to the following:Coordinate the work of engineers from multiple groups to develop Design Rules, Requirements, Test Structures and improve process margin for all DRAM generations.Pro-actively identify and address process issues and process window vs. die size issues stemming from specific database layout or layout techniques.Partner with Design, Product Engineering, Process integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM products.Assure that the right DRC’s (Design Rule Checks) are in place, and assure appropriate reaction to deviation from established design rules.Strategically partner with multiple teams to understand process issues related to the database layout, and prioritize development of solutions.Manage effort to build and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices.Summarize sophisticated problems, derive and explain actions taken to address them.Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment.Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelines.Maintain and implement meaningful communication between Process Integration, Product Engineering, Design, and Advanced Mask teams.Improve timely documentation of the R&D activities with regard to design rule improvements for transfer to parts still in design.Manage, develop, lead, and mentor a group of design rule and design enablement engineers.Minimum Qualifications:MS/PhD in Electrical Engineering, Microelectronics, Physics or related field.Demonstrated experience overseeing an engineering team (5+ direct reports).Senior level (10+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development.Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired.Success in resolving sophisticated issues.Think and communicate clearly in urgent and stressful situations.Possess a deep understanding of the DRAM process flow, as well as the function and purpose of major DRAM components.Exposure and familiarity with CAD group interactions and the process of transferring data from the database to the reticle.Previous experience in R&D for DRAM is preferred.Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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Our vision is to transform how the world uses information to enrich life for
all
.
Check all associated application documentation thoroughly before clicking on the apply button at the bottom of this description.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.Micron has a unique opportunity for a highly experienced DRAM Design Rule Engineer to join our leadership team. As Director - DRAM Design Rule Enablement team, your primary leadership responsibility is to be a catalyst to next-generation DRAM development efforts! We exercise deep knowledge on defining, executing, and coordinating effective actions to enable the project to hit key achievements and timelines.Responsibilities include but are not limited to the following:Coordinate the work of engineers from multiple groups to develop Design Rules, Requirements, Test Structures and improve process margin for all DRAM generations.Pro-actively identify and address process issues and process window vs. die size issues stemming from specific database layout or layout techniques.Partner with Design, Product Engineering, Process integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM products.Assure that the right DRC’s (Design Rule Checks) are in place, and assure appropriate reaction to deviation from established design rules.Strategically partner with multiple teams to understand process issues related to the database layout, and prioritize development of solutions.Manage effort to build and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices.Summarize sophisticated problems, derive and explain actions taken to address them.Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment.Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelines.Maintain and implement meaningful communication between Process Integration, Product Engineering, Design, and Advanced Mask teams.Improve timely documentation of the R&D activities with regard to design rule improvements for transfer to parts still in design.Manage, develop, lead, and mentor a group of design rule and design enablement engineers.Minimum Qualifications:MS/PhD in Electrical Engineering, Microelectronics, Physics or related field.Demonstrated experience overseeing an engineering team (5+ direct reports).Senior level (10+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development.Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired.Success in resolving sophisticated issues.Think and communicate clearly in urgent and stressful situations.Possess a deep understanding of the DRAM process flow, as well as the function and purpose of major DRAM components.Exposure and familiarity with CAD group interactions and the process of transferring data from the database to the reticle.Previous experience in R&D for DRAM is preferred.Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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