Micron Technology, Inc
Senior/Principal Layout Designer - DRAM Design - TPG
Micron Technology, Inc, Atlanta, Georgia, United States, 30349
Our vision is to transform how the world uses information to enrich life for
all .
Read all the information about this opportunity carefully, then use the application button below to send your CV and application.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Our Opportunity Summary:
For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.We are looking for an IP layout engineer in our DRAM and Emerging Memory Group (DEG) at Micron Technology, Inc. As an IP layout engineer, you will be working with an exceptionally hard-working, passionate core team collaborating with peer teams across Micron's global footprint in a multiple projects-based environment. You will be responsible for ensuring that all engineering and process-related criteria/standards needed for an assigned DRAM product are met. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution. This role requires collaboration with our extraordinary DRAM Design group and our other engineering groups to apply multiple layout techniques to design and verify digital and analog circuits. Lastly, you will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tape-out processes and procedures.*This will be a hybrid position located in Atlanta, GAWhat’s Encouraged Daily:
BE/BTech or MTech in Electronic/VLSI Engineering or equivalent.Responsible for the design and development of analog layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check, and documentation.Responsible for on-time delivery of block-level layouts with acceptable quality.Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules/landmarks in multiple project environments.Lead junior team members in their execution of sub sub-block-level layouts & review their work.Contribute to effective project management and technical innovation.Plan and document your layout, presenting material for global teams to review.Connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.How To Qualify:
Must have 10+ years of experience in analog layout designs in sophisticated CMOS processes.Should have expertise in multiple IP layout library developments.Knowledge of DRAM chip architecture is needed.Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.Should have expertise in layout area and routing optimization, design rules, yield, and reliability issues.Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Should have adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power, and area.Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layouts.Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Should have leadership skills and be able to multitask as required.Should be able to work in a team environment and provide technical support to fellow team members.Self-motivated, hardworking, goal-oriented, and possess excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
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all .
Read all the information about this opportunity carefully, then use the application button below to send your CV and application.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Our Opportunity Summary:
For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.We are looking for an IP layout engineer in our DRAM and Emerging Memory Group (DEG) at Micron Technology, Inc. As an IP layout engineer, you will be working with an exceptionally hard-working, passionate core team collaborating with peer teams across Micron's global footprint in a multiple projects-based environment. You will be responsible for ensuring that all engineering and process-related criteria/standards needed for an assigned DRAM product are met. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution. This role requires collaboration with our extraordinary DRAM Design group and our other engineering groups to apply multiple layout techniques to design and verify digital and analog circuits. Lastly, you will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tape-out processes and procedures.*This will be a hybrid position located in Atlanta, GAWhat’s Encouraged Daily:
BE/BTech or MTech in Electronic/VLSI Engineering or equivalent.Responsible for the design and development of analog layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check, and documentation.Responsible for on-time delivery of block-level layouts with acceptable quality.Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules/landmarks in multiple project environments.Lead junior team members in their execution of sub sub-block-level layouts & review their work.Contribute to effective project management and technical innovation.Plan and document your layout, presenting material for global teams to review.Connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.How To Qualify:
Must have 10+ years of experience in analog layout designs in sophisticated CMOS processes.Should have expertise in multiple IP layout library developments.Knowledge of DRAM chip architecture is needed.Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.Should have expertise in layout area and routing optimization, design rules, yield, and reliability issues.Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Should have adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power, and area.Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layouts.Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Should have leadership skills and be able to multitask as required.Should be able to work in a team environment and provide technical support to fellow team members.Self-motivated, hardworking, goal-oriented, and possess excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
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