Western Digital Capital is hiring: ASIC Design Manager in Roseville

Job Type (exemption status): Exempt position - Please see related compensation & benefits details belowSalary Range: 135,660.00-192,100.00Business Function: ASIC Development EngineeringCompany Description At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital, G-Technology, SanDisk and WD brands.Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.Job Description Leadership and Team Management:Lead and manage a team of engineers in the design and development of ASIC (Application-Specific Integrated Circuit) designs.Mentor and coach team members, fostering a collaborative and innovative environment.Manage project schedules, deliverables, and resource allocation to ensure timely and successful completion of design projects.ASIC Design Process Oversight:Manage architecture specification, RTL design, FPGA based emulation and board level hardware development.Oversee physical design activities contracted to a third-party ASIC Vendor, including synthesis, static timing, layout, DFT, DRC/LVS checks, power integrity analysis, test vector generation & ASIC qualification.Collaborate with cross-functional teams (e.g., Architecture, Verification, System test, Hardware, and physical design) to ensure design consistency and integration.Technical Direction and Innovation:Provide technical direction on ASIC architecture, design methodologies, and design best practices.Identify and implement design optimizations for performance, power, and area (PPA).Stay up to date with industry trends and emerging technologies, guiding the team toward innovative solutions.Stakeholder Communication and Collaboration:Coordinate with external ASIC vendors, foundries, and EDA tool providers to ensure design flows and tools are up to standard.Communicate project status, risks, and deliverables to senior management and stakeholders.Support post-silicon activities, including bring-up, validation, and debug.Risk Management and Problem-Solving:Identify potential design risks and work proactively to mitigate them.Resolve design and integration issues that arise during the development cycle.Qualifications Educational Background:Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.Strong understanding of digital design principles, ASIC design methodologies, physical design, and verification.Experience:Minimum of 5 years of experience in ASIC design, including RTL design, synthesis, timing closure, and verification.Proven track record of managing or leading ASIC design projects from conception to tape-out.Hands-on experience with ASIC design tools such as Cadence, Synopsys, or Mentor Graphics.Technical Skills:Proficiency in HDL languages (e.g., Verilog, VHDL) and scripting languages (e.g., Python, Perl, TCL).Understanding of physical design concepts, including synthesis, floor planning, and timing analysis.Knowledge of DFT (Design for Test) and low-power design techniques.Experience with hardware development, post-silicon validation, debug, and bring-up processes.Soft Skills:Strong leadership and people management skills.Excellent communication and collaboration abilities to work with cross-functional teams and external stakeholders.Problem-solving mindset with a keen eye for detail and quality.Additional Preferred Qualifications:Experience with mixed-signal design or working in advanced process nodes (e.g., 7nm, 5nm).Familiarity with system-level architecture and integration, including interface protocols such as PCIe or Ethernet.Knowledge of storage protocols like Fiber Channel, SCSI, SAS, SATA, NVMe or NVMe over fabrics will be a plus.Additional Information Western Digital is committed to providing equal opportunities to all applicants and employees and will not discriminate based on their race, color, ancestry, religion, sex, gender, age, national origin, sexual orientation, medical condition, marital status, physical disability, mental disability, genetic information, protected medical and family care leave, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment.Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution.Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@wdc.com to advise us of your accommodation request.Compensation & Benefits DetailsAn employee’s pay position within the salary range may be based on several factors including but not limited to relevant education, qualifications, certifications, experience, skills, performance, geographic location, and organizational needs.The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. This range may be modified in the future.You will be eligible to participate in Western Digital’s Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance.We offer a comprehensive package of benefits including paid vacation time; medical/dental/vision insurance; life, accident and disability insurance; flexible spending and health savings accounts; employee assistance program; tuition reimbursement; and the Western Digital Savings 401(k) Plan.#J-18808-Ljbffr