Tenstorrent is hiring: SOC Physical Design Lead in Santa Clara

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. This role involves managing full chip and sub-block floor planning, providing essential collaterals for block-level physical implementation. It includes top-level SoC integration, such as power grid, clocking, and bump planning, while working closely with Architecture, RTL, and packaging teams. The position also drives layout verification closure and owns top-level SoC floorplan methodology and tools.

This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Responsible for floor planning of full chip and sub-blocks, delivering floorplan collaterals for block level physical implementation.
• Top-level SoC integration including RDL, power grid, clocking and bump planning.
• Cross discipline collaboration between Architecture, RTL and packaging teams to drive decisions.
• Driving layout verification closure at SoC level.
• Drive and own top-level SoC floorplan methodology and tools.

Experience & Qualifications:

• Minimum BS and 10+ years of experience in Physical Design of SoCs.
• Proven track record of successful tape-outs and meeting performance targets.
• In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, routing, DFM techniques and physical verification.
• Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor.
• Hands-on experience in Power and Signal Integrity analysis.
• Ability to debug and fix LVS, DRC, Antenna, ERC issues.
• Strong communication and teamwork skills, with the ability to lead and collaborate in a cross-functional environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.