Senior ASIC Designer Job at Western Digital Capital in Roseville

Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Salary Range: 125,375.00-177,600.00 Business Function: ASIC Development Engineering Company Description At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too. We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital, G-Technology, SanDisk and WD brands. Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data. Job Description We are seeking a highly skilled and experienced Senior ASIC Designer to join our engineering team. The ideal candidate will have a strong background in both logic design, with extensive Verilog coding experience, and a good understanding of physical design. This role involves designing, developing, and optimizing ASICs for our next-generation products, ensuring high performance, efficiency, and scalability. ESSENTIAL DUTIES AND RESPONSIBILITIES Design and implement complex ASICs using System Verilog Technical oversee of physical design process, including synthesis, floor planning, power grid design, place and route, reset/clock tree synthesis, design for manufacturability and timing closure. Collaborate with cross-functional teams to define design specifications and requirements. Optimize designs for power, performance, and area (PPA). Micro-architecture of the modules you will be responsible for Work with verification teams to review the test plans and provide input Debug, root cause and fix issues found in the design as part of verification testing based on simulations or FPGA testing. Stay abreast of the latest ASIC design technologies and methodologies. Qualifications REQUIRED Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. A Master's degree is preferred. Minimum of 10 years of professional experience in ASIC design, with a strong focus on logic design and good understanding of physical design Proficient in Verilog and System Verilog for RTL design and verification. Experience with ASIC design tools and methodologies, including EDA tools for synthesis, place and route, and timing analysis (e.g., Cadence, Synopsys). Deep understanding of digital design principles, including FSMs, data path architectures, and low power design techniques. Good understanding of physical design and related challenges, such as DFM (Design for Manufacturability), signal integrity, and power integrity. Experience with scripting languages such as Python or Perl for design automation. Strong analytical and problem-solving skills, with the ability to think creatively to overcome design challenges. Excellent communication and teamwork skills, with the experience leading projects and mentoring junior designer SKILLS Knowledge of FPGA design and prototyping. Experience with analog design integration and mixed-signal design considerations. Familiarity with industry standards and protocols relevant to the company's products. Participation in silicon bring-up, validation, and debugging Knowledge of TCP/IP, RoCE, RDMA Protocols, Ethernet, PCIe, TLS, IPSec and NVMe Design Experience with Cryptography, Root of Trust (RoT) items like Secure Boot, Secure Firmware Download, Secure Debug, Authentication and Attestation Additional Information Western Digital is an equal opportunity employer. We do not discriminate against any applicant or employee based on race, color, ancestry, religion, sex, gender, age, national origin, sexual orientation, medical condition, marital status, physical or mental disability, genetic information, military and veteran status, or any other legally protected characteristics. Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@wdc.com to advise us of your accommodation request. Based on our experience, we anticipate that the application deadline will be 01/11/2025 . However, we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. Compensation & Benefits Details An employee’s pay position within the salary range may be based on several factors including relevant education, qualifications, certifications, experience, skills, and geographic location. The salary range is applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in these states. You will be eligible to participate in Western Digital’s Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. We offer a comprehensive package of benefits including paid vacation time, medical/dental/vision insurance, life insurance, and the Western Digital Savings 401(k) Plan. #J-18808-Ljbffr