SMTS, Design Rule Enablement Team Job at Idaho State Job Bank in Boise

SMTS, Design Rule Enablement Team at Micron Technology, Inc. in Boise, Idaho, United States Job Description Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design Enablement Team (DET) Manager Responsibilities include but not limited to the following + Manage a team of Design Enablement Leads (DELs) who coordinate electrical test structure development, build and evaluation for future DRAM nodes and quantify process margin on current devices + Define milestones for projects within the layout schedule and work with the various teams to achieve the targets and time-lines + Partner with Design, Product Engineering, Process integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM products + Strategically partner with multiple teams and fields to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design + Summarize sophisticated problems, derive and explain actions taken to address them + Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment + Maintain and implement meaningful communication between Process Integration, Product Engineering, Design, and Advanced Mask teams + Improve timely documentation of the R&D activities with regard to design rule improvements for transfer to parts still in design + DFM, pitch cell improvement, etc. for test structure. Validate and improve existing design rule by using test structure char and analysis. Minimum Qualifications + BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field + Senior level (10+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development + Electrical test structure layout and characterization experience + Process integration or Design or Product Engineering experience a plus + Able to manage complex programs across multiple geographies and different cross-functional groups. + Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired + Success in resolving sophisticated issues + Thin To view full details and how to apply, please login or create a Job Seeker account