Director, HBM SoC Design - TPG Job at Micron Memory Malaysia Sdn Bhd in Dallas

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Opportunity Summary: For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. As the Director of HBM SoC Design, you will lead a team of HBM SoC Design Engineers within the Heterogeneous Integration Group (HIG). Your team will be responsible for the design, development, and integration of digital and analog circuits, including complex IP blocks. This role involves simulating, optimizing, and floor planning various blocks. You will collaborate with Micron’s global design and verification teams and support groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to proactively design HBM products that optimize manufacturing functions and ensure the best performance, power, cost, quality, reliability, time-to-market, and customer satisfaction. In HBM DEG (High Bandwidth Memory - DRAM Engineering Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most challenging due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting. Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity. What’s Encouraged Daily: Develop innovative HBM solutions with new memory subsystem frameworks targeting AI/ML applications. Lead the design and development of HBM base die SoC solutions, including top-level design, verification, and integration of various IP blocks. Ensure HBM products are best-in-class for speed, power, cost, quality, and reliability by collaborating with HBM engineering teams. Work with HBM Engineering, Marketing, Probe, Assembly, Test, Process Integration, and Manufacturing groups to ensure proper manufacturability of products. Lead and collaborate with physical design, layout, and verification teams to deliver high-quality, on-time deliverables, including initial tape-out and design revisions. Debug and identify root causes and solutions for pre-silicon and post-silicon issues in HBM products. Create architectural specifications and external-facing documents, working with partners to generate specifications considering various hardware and protocol standards. Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure design quality. Foster cross-group communication to work towards standardization and group success. Attract, recruit, train, engage, and retain top talent to build a world-class HBM SoC design team. Challenge the team to set and achieve stretch objectives while focusing on continuous improvement in schedules, quality, and capability. Build a team culture of hard work, innovation, and strong global collaboration with a focus on Micron’s Values. How To Qualify: Proven experience leading highly technical SoC design teams in a multinational design center model with multiple successful tape-outs to advanced logic foundries such as TSMC. Familiarity with the full cycle of SoC development, from architectural spec development to frontend and backend design, verification, and post-silicon bring-up. Experience working with IP providers and seamlessly integrating complex IP from third parties into the SoC, ensuring smooth pre-silicon and post-silicon engagement. This includes PHY, memory controllers, NOC, microcontrollers, MBIST, interfaces, adapters, RAS, buffers, etc., for various memory types (DDR, LPDDR, HBM). Strong RTL development capabilities and familiarity with IP level verification, synthesis, STA, and logic equivalence. Knowledge of DRAM operation, preferably with the HBM product family. Proficiency with various EDA tools from Cadence, Synopsys, or Mentor Graphic, etc. Experience with programming languages and scripting (e.g., Verilog, VHDL, SystemVerilog, Python). Knowledge of industry standards and compliance requirements (e.g., JEDEC, ISO 26262, etc). What Sets You Apart: Minimum 15 years of experience in a related field. Bachelor’s degree in a relevant field. Strong analytical and problem-solving skills. Experience in project management methodologies. Proven ability to mentor and develop junior engineers. Strong collaboration, adaptability, and effective communication skills. Ability to work in a fast-paced, dynamic environment and manage multiple priorities. #J-18808-Ljbffr