Canvendor is hiring: Memory Controller Designer (RTL) in Austin

Position: Memory Controller Designer/RTL Engineer Location: Austin, TX / San Jose, CA (Hybrid) Type: Contract Key responsibilities include: Drive the timely development and debug of new features on timely development of custom memory controller. Working on SOC IP delivery with all sanity checks. Work on timing debug and closure. Working on LINT, CDC flows and analysis. Work on power artist flow and power analysis. Working on ECO flows. Work with the verification team to verify the functionality and correctness of the design. Collaborate with implementation to achieve your timing and area. Produce quality RTL on schedule meeting PPA goals Engage with performance and power team on achieving performance and power goals. Partner with the physical design and CAD team to resolve implementation level details. Requirements PhD, Master’s Degree or Bachelor’s Degree, Computer Engineer with over 10 years of experience. Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis & ECO. Knowledge of memory controller u-architecture. Familiarity with different memory technologies like LPDDR4/5, HBM. Knowledge of JEDEC memory standards preferred. Knowledge of AES, ECC, RAS features preferred. Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team. Experience with a scripting language like Perl or Python. Energetic, curiosity, and passion in logic design. Good written and verbal communication skills.