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Veear

Physical Design - STA Mid-Level

Veear, Santa Clara, CA, United States

Job Description:
  • Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
  • Hands-on experience on Logical Aware Synthesis, Logical Equivalence check and Static Timing analysis.
  • Hands-on the DMSA flow to fix pre and post STA timing.
  • Knowledge on the Timing closure on Sub system level & Block level and Chip level.
  • Knowledge on Writing Manual ECO's to fix timing violations and DRC's.
  • Knowledge on constraint development.
  • Good Knowledge of TCL scripting and UNIX env.
  • Leading team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.
  • Should Co-ordinate with design team counterparts in RTL design, Physical design and DFT.
  • Good communication skills and client interface role.