Tara Technical Solutions (TTS) is hiring: Design For Test in San Jose

DFT for ASIC & SOC IP- FULL-TIME- SAN JOSE- Direct Hire.

Senior Or Principal Titles-

Key Responsibilities:

• Implement and verify DFT methodologies specifically for ASIC SoC IP Design.
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• Collaborate with design and architecture teams to identify and define critical testability requirements.
• Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.
• Analyze DFT-related data and provide insights for continuous design improvements.
• Document verification processes, results, and best practices to enhance team knowledge and efficiency.
• Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.
• Working closely with STA and DI Engineers design closure for test
• Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customers, physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 3nm IPs & beyond
• Automating DFT & Test Vector Generation flows.

 Skills/Experience: 

• Strong DFT background.
• Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.
• Understanding of DFT methodologies, including scan, BIST, and ATPG.
• Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).

• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Excellent problem solving, debug , root cause analysis and communication skills
• Experience working on ATE is a plus.
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• Familiarity with BIST logic for array and link testing is a plus.
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• Knowledge of AHB/APB/AXI buses is a plus