DIRECTOR MEMORY PHY DESIGN VERIFICATION TECHNICAL LEAD Job at AMD in Folsom
AMD, Folsom, CA, United States, 95630
DIRECTOR MEMORY PHY DESIGN VERIFICATION TECHNICAL LEAD
This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
The Role
We are searching for a senior leader to lead state of the art next generation memory PHY IP design verification. The candidate will work closely with the architecture team, design team, SOC, FW, and post silicon teams to achieve successful IP delivery to all AMD products across all business units.
The Person
The successful candidate will possess:
- Proven track record of executing and delivering all validation aspects of Memory PHY and mixed signal IPs
- Good technical knowledge and experience of high-speed IO circuits and Memory PHYs as DDR/LPDDR/GDDR/HBM.
- Strong and effective communication skills with teams and customers worldwide
- Effective at leading and getting results
Key Responsibilities
- Lead verification strategy and provide technical direction to next generation memory PHY IPs as next generation MRDIMM and DDR6
- Verification of PHY design and PHY firmware
- Support testchip SOCs to drive new standards
- Support Post-Si teams for Product Performance, Power, and functional issues debug/resolution
- Comprehend AMS, Firmware, and design spec. Work with other functional leads to come up with a DV plan and execute the plan
- Create, guide and review UVM/System Verilog based testbenches and tests
- Lead Formal verification
Preferred Experience
- Memory PHY verification experience
- Deep knowledge of all aspects of mixed signal IP pre-silicon and post-silicon validation
- Formal verification expertise
- Firmware verification experience
- Excellent communication, management, and presentation skills
- Collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
Academic Credentials
- Relevant academic background (Master/PhD degree preferred)