RTL ASIC Design Design/ Architecture design

1. Role: RTL ASIC Design Design/ Architecture design (TA ArunNR)

Location: Sunnyvale
Fulltime only
Exp: 8 to 15 years
Salary: 170K to 200K max

• Architecture and microarchitecture of System on a Chip ("SOC") subsystems, Intellectual Property Functional Blocks ("IPs"), sub-IPs, modules, and library components
• Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis ("HLS"). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components
• SoC-level integration
• Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation
• Design for low power and power intent design using Unified Power Format ("UPF")
• Constraint development, synthesis, timing closure, and optimization of the design
• Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing
• Debug and bug fixes
• Exp in Lint, CDC, spyglass tool is preferred.

Diverse Lynx LLC is an Equal Employment Opportunity employer. All qualified applicants will receive due consideration for employment without any discrimination. All applicants will be evaluated solely on the basis of their ability, competence and their proven capability to perform the functions outlined in the corresponding role. We promote and support a diverse workforce across all levels in the company.