Verification Engineer_SUC-SEM-25-01

Summary: The main function of the Verification Engineer is to work with a group of researchers and engineers to own the electrical system level verification of various products. Working closely with researchers, architects, and designers in architecting methods of electrical verification for multiple state of the art systems. Using verification skills to define verification requirements, create test cases, design, and implement the testing infrastructure, execute the testing, and report the results for the new product designs. Role Responsibilities: Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams Define and track detailed test plans for the different modules and top-level systems Define, architect, design, and drive implementation of scalable test infrastructure Keep track of coverage metrics and bugs encountered and fixed Own execution, interpretation, and reporting of electrical system level verification work status and results Support system bring up and debug activities Clearly communicate test plans and results Must-Have Skills: Strong System Verilog, debugging skills, experience owning areas of product verification 5-10 years of experience working as a verification engineer Proficient with UVM and integration verification Nice-to-Have Skills: Experience with Python Experience with CC++ Education/Experience: Bachelor’s degree in electrical engineering, Computer Science, or equivalent experience 5-10 years of experience working as a verification engineer