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Rival

Cache Microarchitecture & Logic Design

Rival, Austin

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Positions are open for full-time in the areas of Cache microarchitecture and logic design.

Responsibilities
  • As a Cache Microarchitecture & Logic Design Engineer, you will own or participate in the following:
  • Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification.
  • Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals.
  • Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.
  • Validation - support test bench development and simulation for functional and performance verification.
  • Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance.
Requirements
  • Thorough knowledge of microprocessor or SOC design with 2+ years of direct work experience in one or more of the following areas:
  • High performance cache controllers - pipeline design, hazard detection, parity/ECC generation, coherency policies, replacement policies.
  • Coherent on-chip Fabrics for high performance SOCs and design of associated control structures.
  • Knowledge of SystemVerilog.
  • Experience with simulators and waveform debugging tools.
  • Knowledge of logic design principles along with timing and power implications.
  • Understanding of low power microarchitecture techniques.
  • Understanding of high performance techniques and trade-offs in a CPU microarchitecture.
  • Experience in C or C++ programming.

Education and Experience

PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

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