Packaging Designer Job at Tara Technical Solutions (TTS) in San Mateo
Tara Technical Solutions (TTS), San Mateo, CA, United States, 94409
Senior Packaging experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs .
FULL-TIME- Direct Hire-- Fortune 500 Client-
San Jose OR Austin Or Fort Collins.
Developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations.
RESPONSIBILITIES:
Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest (3 or more years is preferred)
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
General flip-chip BGA package design & engineering
Project management and customer interface for your design projects
Contribute to efficiency improvements for the design
EDUCATION/EXPERIENCE & REQUIREMENTS:
BSEE or similar field and 8+ years experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years experience in flip-chip-BGA package design, including high-speed SerDes
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
Self-management and organization skills.