United Software Group Inc. - US West
RTL ASIC Front End Designer
United Software Group Inc. - US West - Sunnyvale, California, United States, 94087
Work at United Software Group Inc. - US West
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Overview
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Job Title: RTL ASIC Front End Designer
Location: Sunnyvale, CA or Austin, TX
Fulltime only
Keywords:
RTL ASIC design, SOC design, IP design, Lint, CDC, RTL Architecture design Job Description: Architecture and microarchitecture of System on a Chip (“SOC”) subsystems, Intellectual Property Functional Blocks (“IPs”), sub-IPs, modules, and library components. Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (“HLS”). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components. SoC-level integration. Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation. Design for low power and power intent design using Unified Power Format (“UPF”). Constraint development, synthesis, timing closure, and optimization of the design. Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing. Debug and bug fixes. Experience in Lint, CDC, spyglass tool is preferred. Thanks & Regards, Ranjith Kumar Vemula Account Manager Phone:
614-588-8525/ 614-495-9222 Ext: 261 | Fax: 866-764-1148
Want to apply Read all the information about this position below, then hit the apply button. Email ID:
Ranjith.vemula@usgrpinc.com
#J-18808-Ljbffr
RTL ASIC design, SOC design, IP design, Lint, CDC, RTL Architecture design Job Description: Architecture and microarchitecture of System on a Chip (“SOC”) subsystems, Intellectual Property Functional Blocks (“IPs”), sub-IPs, modules, and library components. Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (“HLS”). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components. SoC-level integration. Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation. Design for low power and power intent design using Unified Power Format (“UPF”). Constraint development, synthesis, timing closure, and optimization of the design. Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing. Debug and bug fixes. Experience in Lint, CDC, spyglass tool is preferred. Thanks & Regards, Ranjith Kumar Vemula Account Manager Phone:
614-588-8525/ 614-495-9222 Ext: 261 | Fax: 866-764-1148
Want to apply Read all the information about this position below, then hit the apply button. Email ID:
Ranjith.vemula@usgrpinc.com
#J-18808-Ljbffr