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Key Responsibilities: Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization for ASIC blocks. Use Cadence iSpatial to establish a unified synthesis-to-place-and-route flow for efficient physical implementation. Ensure timing closure using Tempus STA, resolving setup, hold, clock skew, and noise violations. Apply physical constraints, including placement constraints, routing blockages, and power grid definition. Work on congestion analysis, IR drop analysis, and signal integrity optimization to meet design signoff requirements. Conduct physical verification (DRC, LVS, antenna checks) and implement necessary fixes. Collaborate with RTL designers, DFT engineers, and verification teams to ensure seamless integration. Perform Engineering Change Order (ECO) implementation to address functional and timing updates. Develop and enhance automation scripts (TCL, Python, Perl) for workflow efficiency. Optimize power planning strategies to minimize leakage and dynamic power. Keep up to date with Cadence tool advancements and apply best practices in leading-edge node technologies (e.g., 7nm, 5nm, 3nm FinFETs). Required Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, VLSI, or a related field. 5+ years of hands-on experience in ASIC Place & Route using Cadence Genus, Innovus, Tempus, and iSpatial flows. Strong expertise in timing analysis, static timing closure, and signoff methodologies. Proficiency in floorplanning, placement, CTS, and routing optimizations. Experience with power planning, IR drop mitigation, and clock tree balancing. Familiarity with Cadence Quantus for extraction and Pegasus/Calibre for physical verification. Strong scripting skills (TCL, Python, Perl) to automate design tasks. Understanding of DFT integration and multi-mode, multi-corner optimization strategies. Ability to work in a fast-paced, cross-functional team environment. Preferred Qualifications: Experience with leading-edge finfet process nodes (16nm, 12nm, 5nm, 3nm, or below).