Piper Companies
RTL Design Director
Piper Companies - Saratoga, California, us, 95071
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Overview
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Overview
Piper Companies is hiring a RTL Design Director for a small networking start up company based in Saratoga, CA. The RTL Design Director will need to have experience building out teams (hiring, firing, mentoring, training, etc.) as well as currently be hands on.
The RTL Design Director will need to sit on site in Saratoga, CA 5 days per week. This role is not able to provide sponsorship.
Responsibilities of the RTL Design Director:
Lead the design and development of RTL for complex ASIC chips. Provide hands-on expertise in RTL coding, synthesis, and design verification. Build and manage a high-performing team of RTL designers and engineers. Develop and implement design methodologies and best practices. Work closely with hardware and software teams to optimize design performance. Ensure designs meet timing, power, and area constraints. Conduct design reviews and provide technical guidance to the team. Stay up-to-date with industry trends and emerging technologies. Requirements of the RTL Design Director:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design and development for complex ASIC chips. Strong hands-on expertise in Verilog, VHDL, and SystemVerilog. Extensive experience with Ethernet switches and bridges. Demonstrated ability to build and lead high-performing design teams. In-depth knowledge of synthesis, timing analysis, and design verification. Familiarity with EDA tools and design methodologies. Excellent problem-solving and analytical skills. Strong communication and leadership abilities. Compensation of the RTL Design Director:
$275,000 - $350,000 Full Comprehensive Benefits: Health, Vision, Dental, PTO, Holiday, Sick Leave if required by law
Keywords: Verilog, VHDL, FPGA, ASIC, RTL coding, synthesis, timing analysis, design verification, DFT, Design for Testability, SystemVerilog, UVM, Universal Verification Methodology, EDA tools, Electronic Design Automation, RTL optimization, HDL, Hardware Description Language, logic design, power analysis, floorplanning, clock domain crossing, RTL linting, sign-off, chip design, RTL synthesis, RTL design flow, RTL simulation, RTL coding styles
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The RTL Design Director will need to sit on site in Saratoga, CA 5 days per week. This role is not able to provide sponsorship.
Responsibilities of the RTL Design Director:
Lead the design and development of RTL for complex ASIC chips. Provide hands-on expertise in RTL coding, synthesis, and design verification. Build and manage a high-performing team of RTL designers and engineers. Develop and implement design methodologies and best practices. Work closely with hardware and software teams to optimize design performance. Ensure designs meet timing, power, and area constraints. Conduct design reviews and provide technical guidance to the team. Stay up-to-date with industry trends and emerging technologies. Requirements of the RTL Design Director:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design and development for complex ASIC chips. Strong hands-on expertise in Verilog, VHDL, and SystemVerilog. Extensive experience with Ethernet switches and bridges. Demonstrated ability to build and lead high-performing design teams. In-depth knowledge of synthesis, timing analysis, and design verification. Familiarity with EDA tools and design methodologies. Excellent problem-solving and analytical skills. Strong communication and leadership abilities. Compensation of the RTL Design Director:
$275,000 - $350,000 Full Comprehensive Benefits: Health, Vision, Dental, PTO, Holiday, Sick Leave if required by law
Keywords: Verilog, VHDL, FPGA, ASIC, RTL coding, synthesis, timing analysis, design verification, DFT, Design for Testability, SystemVerilog, UVM, Universal Verification Methodology, EDA tools, Electronic Design Automation, RTL optimization, HDL, Hardware Description Language, logic design, power analysis, floorplanning, clock domain crossing, RTL linting, sign-off, chip design, RTL synthesis, RTL design flow, RTL simulation, RTL coding styles
#LI-AG1
#ONSITE