Advanced Micro Devices
Sr. Manager Digital Design-Mixed Signal IP
Advanced Micro Devices - San Jose, California, United States, 95123
Work at Advanced Micro Devices
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Overview
WHAT YOU DO AT AMD CHANGES EVERYTHING
Are you the right candidate for this opportunity Make sure to read the full description below. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. THE ROLE: AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate an expert team. You will manage a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies. THE PERSON: The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBILITIES: Experience successfully leading small to medium size digital design mixed signal IP engineering teams. Able to lead a team effectively, excellent interpersonal and team building skills. Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective negotiation/ technical and management communication at the peer and upward management levels. Strong experience in RTL/ Digital Design engineering team management. Effective delegation and coaching skills. Proven experience managing and leading engineering teams. Proven ability to lead successful digital or mixed signal IP developments to high volume production. Experience with SerDes or DDR PHY digital logic layer implementation is a must. Direct chip design experience in DDR memory products is a strong plus. Experience with digital design methodologies for clock domain checks, reset checks and low power design. Domain knowledge in memory sub-systems/PHYs, Buses/Fabric, Debug/Trace, Interrupts, or Clocks/Reset. Experience with complicated static timing analysis (STA) timing constraints including multiple clocks, both asynchronous and synchronous. Experience with designs with multiple clocks and both asynchronous and synchronous data handoffs. Experience with high speed digital design. Knowledge of ASIC Verification, DFT, synthesis, STA/timing closure, Knowledge of high performance and low-power design techniques. Very good understanding, DFT flow (SCAN/IDDQ/MBIST), physical design and IR drop. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Experience in the development of ATE patterns for digital and mixed-signal designs, and support of ATE activity including test pattern debug and test time reduction. Experience with embedded FW development is an added advantage. Strong organization and communication skills and ability to establish lasting relationships and networks. Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments. Strong communications skills. Able to summarize complex problems for upper management as well as drill down to details with architects and engineers. Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices. PREFERRED EXPERIENCE: High judgement individual providing technical leadership and direction for a mixed signal IP (MSIP) FrontEnd design team. Experience leading and managing a team of FrontEnd/RTL/logic+hardware silicon designers. Collaborate with SOC/Sub-System Architects to translate high level architecture requirements into microarchitecture and design implementation. Contribute to the definition of the MSIP microarchitecture, circuit architecture, and digital sub-systems blocks. Responsibilities include high level design planning, work breakdown planning, tasks assignments and progress tracking, schedule and priority management, performance review, mentor, talent development, and hiring. As FrontEnd team lead, work with mixed-signal IP director, project-manager, mixed-signal IP architects, circuit/AMS and physical design leads to guarantee quality/timely deliverables meeting schedule and technical requirements. Ensure quality of work within committed schedule and proactively managing for critical path and overall risk. Effectively collaborate with various mixed-signal IP domains (e.g. Analog Design, Custom Digital Design, AMS Circuit Architecture and AMS Design Verification, Functional Verifications) across different geographies, to ensure successful cross-team alignment, engagement and high-quality execution. Proven track record of successfully taking designs to production. Contribute to the definition of frontend dev flows toward improving efficiency, efficacy and quality of execution. Manage and enforce design flows best practices to guarantee design meets committed bounding box for performance, power, reliability and timing requirements. Work closely with the physical design/DFX teams to deliver GDSII design. Influence development of methodologies for best in-class/best PPA designs. Set and enforce quality standards for FrontEnd design and development. Co-own post-silicon planning activities such as initial bring-up, platform validation, characterization, parameter optimization, and final productization (Performance, Power, Functionality, ..). Define IP production/bench-level test characterization and validation plans working with post-silicon characterization and validation groups. Enable/support teams’ post-Silicon workstream all the way to new product introduction. ACADEMIC CREDENTIALS: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on digital systems architecture. LOCATION:
San Jose, California
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Are you the right candidate for this opportunity Make sure to read the full description below. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. THE ROLE: AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate an expert team. You will manage a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies. THE PERSON: The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBILITIES: Experience successfully leading small to medium size digital design mixed signal IP engineering teams. Able to lead a team effectively, excellent interpersonal and team building skills. Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective negotiation/ technical and management communication at the peer and upward management levels. Strong experience in RTL/ Digital Design engineering team management. Effective delegation and coaching skills. Proven experience managing and leading engineering teams. Proven ability to lead successful digital or mixed signal IP developments to high volume production. Experience with SerDes or DDR PHY digital logic layer implementation is a must. Direct chip design experience in DDR memory products is a strong plus. Experience with digital design methodologies for clock domain checks, reset checks and low power design. Domain knowledge in memory sub-systems/PHYs, Buses/Fabric, Debug/Trace, Interrupts, or Clocks/Reset. Experience with complicated static timing analysis (STA) timing constraints including multiple clocks, both asynchronous and synchronous. Experience with designs with multiple clocks and both asynchronous and synchronous data handoffs. Experience with high speed digital design. Knowledge of ASIC Verification, DFT, synthesis, STA/timing closure, Knowledge of high performance and low-power design techniques. Very good understanding, DFT flow (SCAN/IDDQ/MBIST), physical design and IR drop. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Experience in the development of ATE patterns for digital and mixed-signal designs, and support of ATE activity including test pattern debug and test time reduction. Experience with embedded FW development is an added advantage. Strong organization and communication skills and ability to establish lasting relationships and networks. Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments. Strong communications skills. Able to summarize complex problems for upper management as well as drill down to details with architects and engineers. Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices. PREFERRED EXPERIENCE: High judgement individual providing technical leadership and direction for a mixed signal IP (MSIP) FrontEnd design team. Experience leading and managing a team of FrontEnd/RTL/logic+hardware silicon designers. Collaborate with SOC/Sub-System Architects to translate high level architecture requirements into microarchitecture and design implementation. Contribute to the definition of the MSIP microarchitecture, circuit architecture, and digital sub-systems blocks. Responsibilities include high level design planning, work breakdown planning, tasks assignments and progress tracking, schedule and priority management, performance review, mentor, talent development, and hiring. As FrontEnd team lead, work with mixed-signal IP director, project-manager, mixed-signal IP architects, circuit/AMS and physical design leads to guarantee quality/timely deliverables meeting schedule and technical requirements. Ensure quality of work within committed schedule and proactively managing for critical path and overall risk. Effectively collaborate with various mixed-signal IP domains (e.g. Analog Design, Custom Digital Design, AMS Circuit Architecture and AMS Design Verification, Functional Verifications) across different geographies, to ensure successful cross-team alignment, engagement and high-quality execution. Proven track record of successfully taking designs to production. Contribute to the definition of frontend dev flows toward improving efficiency, efficacy and quality of execution. Manage and enforce design flows best practices to guarantee design meets committed bounding box for performance, power, reliability and timing requirements. Work closely with the physical design/DFX teams to deliver GDSII design. Influence development of methodologies for best in-class/best PPA designs. Set and enforce quality standards for FrontEnd design and development. Co-own post-silicon planning activities such as initial bring-up, platform validation, characterization, parameter optimization, and final productization (Performance, Power, Functionality, ..). Define IP production/bench-level test characterization and validation plans working with post-silicon characterization and validation groups. Enable/support teams’ post-Silicon workstream all the way to new product introduction. ACADEMIC CREDENTIALS: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on digital systems architecture. LOCATION:
San Jose, California
#J-18808-Ljbffr