(2025 New Grads)-Wireline Serdes Analog Mixed Signal Design
MediaTek - Irvine, California, United States
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Overview
Location:
Irvine, California (On-site)
Job Description Architecture study and evaluation of advanced high speed SerDes topologies Design and verification of high-speed high-performance analog and mixed signal circuits including, but not limited to drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc. Collaborate with cross functional teams to improve system performance and optimize designs Evaluate, measure, and debug silicon until it reaches high volume production.
Requirement Student graduated after December 2024 or in 2025 with a M.S. or higher degree in Electrical Engineering or a related field in Physics. Solid background in high-speed analog CMOS circuit design Good understanding of deep submicron process Familiar with serial links and wireline transceivers design and verification. Proficient with Cadence design environment and mixed-signal simulation. Able to assume responsibility for a variety of technical tasks and to work independently Excellent working attitude and good interpersonal and communication skills.
Salary range:
$145,000 - $220,000 annually Actual compensation within that range will be dependent upon the individual's skills, experience, qualifications. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.