Analog Bits
SERDES and Mixed-Signal Layout-Mask Designer
Analog Bits, Sunnyvale, California, United States, 94087
In this position you will play a key role in contributing to the development of advanced mixed signal layout for low power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low power consumer SOCs.
You will join a highly collaborative team, and your success will have a significant impact on our products.
Candidate should have an interest in all the "Key Qualifications" listed, and significant experience in some of them.
Key Qualifications:
At least 5 years of hands on layout design experienceExperience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET processExperience using layout design and verification toolsExperience in floor planning, power grid design, signal routing and repeatersGood understanding of clock routing and shieldingGood understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heatingAbility to learn and ramp on new tools and methodologiesAbility to estimate realistic schedule, track and report clear progress and statusExcellent team player and work closely with the circuit design teamDescription:
Layout design of advanced SERDES and other analog and mixed signal macros in deep Sub-Micron Fin-FET technologiesTasks include planning and implementing block and top level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layoutDRC, LVS and other physical verification toolsParticipate in post-layout circuit performance analysisEstimate and track schedulesEducation:
Layout design diploma or an electrical engineering degree
Base Salary Ranges:
4 - 7 years experience: $75,000.00 - $110,000.008+ years experience: $110,000.00 - $160,000.00
We are an equal opportunity employer and value diversity in our workforce. All employment decisions are made on the basis of qualifications, ability, and business requirements.
You will join a highly collaborative team, and your success will have a significant impact on our products.
Candidate should have an interest in all the "Key Qualifications" listed, and significant experience in some of them.
Key Qualifications:
At least 5 years of hands on layout design experienceExperience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET processExperience using layout design and verification toolsExperience in floor planning, power grid design, signal routing and repeatersGood understanding of clock routing and shieldingGood understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heatingAbility to learn and ramp on new tools and methodologiesAbility to estimate realistic schedule, track and report clear progress and statusExcellent team player and work closely with the circuit design teamDescription:
Layout design of advanced SERDES and other analog and mixed signal macros in deep Sub-Micron Fin-FET technologiesTasks include planning and implementing block and top level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layoutDRC, LVS and other physical verification toolsParticipate in post-layout circuit performance analysisEstimate and track schedulesEducation:
Layout design diploma or an electrical engineering degree
Base Salary Ranges:
4 - 7 years experience: $75,000.00 - $110,000.008+ years experience: $110,000.00 - $160,000.00
We are an equal opportunity employer and value diversity in our workforce. All employment decisions are made on the basis of qualifications, ability, and business requirements.