TSMC
Technical Manager, Physical Design (ASIC/SoC Place & Route) (San Jose, CA)(5572)
TSMC, San Jose, California, United States, 95123
Overview Of Role
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As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PDV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC blocks. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, San Jose, CA and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 3 days in office.
ResponsibilitiesComplete entire physical implementation of the block level and tapeout production chipBlock level floorplan with the ability to analyze the quality of the floorplanCustomized Clock tree structure and Place & RouteImplement ECOs for timing closureSignal EM/Noise and Power IR/EM analysis and fixDRC/LVS/ERC/ANTENNA analysis and clean upPhysical verification sign off
Minimum QualificationsMaster’s degree in Electrical/Computer Science Engineering with 12+ years of industry experience, or Bachelor’s degree in Electrical/Computer Science Engineering plus 18+ years of industry experienceNetlist (or RTL)-GDS physical implementation experienceIn depth knowledge of major EDA tools/design flowsExperience with TSMC N16 or below technologyExperience in block level implementation or chip integration and signoffExperience in Perl/TCL language programmingAbility to work regularly at a Customer site in the South Bay area
Preferred QualificationsTSMC N5 and below technologyLow-power implementation methodologyAdvanced timing signoff methodologyAble to independently complete Netlist-GDS P&R, signoff taskProven record in multi-million gate design production tapeouts
Company DescriptionAs a trusted technology and capacity provider, TSMC is driven by the desire to be:The world’s leading dedicated semiconductor foundryThe technology leader with a strong reputation for manufacturing excellenceAdvancing semiconductor manufacturing innovations to enable the future of technologyTSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.
Diversity StatementTSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at G_Accomodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
Pay Transparency StatementAt TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $129,500 and $130,000. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits. We also offer extensive development opportunities and programs.
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Want to apply Read all the information about this position below, then hit the apply button.
As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PDV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC blocks. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, San Jose, CA and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 3 days in office.
ResponsibilitiesComplete entire physical implementation of the block level and tapeout production chipBlock level floorplan with the ability to analyze the quality of the floorplanCustomized Clock tree structure and Place & RouteImplement ECOs for timing closureSignal EM/Noise and Power IR/EM analysis and fixDRC/LVS/ERC/ANTENNA analysis and clean upPhysical verification sign off
Minimum QualificationsMaster’s degree in Electrical/Computer Science Engineering with 12+ years of industry experience, or Bachelor’s degree in Electrical/Computer Science Engineering plus 18+ years of industry experienceNetlist (or RTL)-GDS physical implementation experienceIn depth knowledge of major EDA tools/design flowsExperience with TSMC N16 or below technologyExperience in block level implementation or chip integration and signoffExperience in Perl/TCL language programmingAbility to work regularly at a Customer site in the South Bay area
Preferred QualificationsTSMC N5 and below technologyLow-power implementation methodologyAdvanced timing signoff methodologyAble to independently complete Netlist-GDS P&R, signoff taskProven record in multi-million gate design production tapeouts
Company DescriptionAs a trusted technology and capacity provider, TSMC is driven by the desire to be:The world’s leading dedicated semiconductor foundryThe technology leader with a strong reputation for manufacturing excellenceAdvancing semiconductor manufacturing innovations to enable the future of technologyTSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.
Diversity StatementTSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at G_Accomodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
Pay Transparency StatementAt TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $129,500 and $130,000. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits. We also offer extensive development opportunities and programs.
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