Tenstorrent Inc
Physical Design Staff, Physical Design Engineeer - LEC Santa Clara, California,
Tenstorrent Inc, Santa Clara, California, us, 95053
Be a part of a dynamic Physical Design team working on high-performance designs going into industry leading AI/ML architecture. This role involves performing Logic Equivalence Checks (LEC) to ensure functional consistency between RTL and gate-level netlists, along with debugging and resolving equivalence issues. The candidate will work closely with front-end design teams and engage in physical design tasks such as synthesis, PnR, and timing closure. A strong background in digital design, RTL coding, and experience with industry-standard EDA tools is essential.
Are you ready to apply Make sure you understand all the responsibilities and tasks associated with this role before proceeding.This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.Responsibilities:
Perform Logic Equivalence Check (LEC) to ensure functional consistency between RTL and gate-level netlists.Work closely with front-end design teams to understand design specifications and constraints.Debug and resolve equivalence check issues, including formal verification failures and synthesis mismatches.Provide feedback and recommendations to improve design flows and methodologies for LEC.Document logical equivalence verification processes, methodologies, and results.Perform physical design tasks including synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning, and power optimization.Utilize industry-standard EDA tools for synthesis, LEC, PnR, and timing closure tasks.Experience & Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.5+ years of experience in physical design and verification, with a focus on LEC.Strong understanding of digital design principles, RTL coding, and synthesis.Hands-on experience with synthesis, block and chip level implementation with industry-standard PnR flows and tools.Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.Solid knowledge of scripting languages (e.g., Python, Tcl, Perl) for automation tasks.Excellent problem-solving skills and attention to detail.Strong communication and teamwork skills.
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Are you ready to apply Make sure you understand all the responsibilities and tasks associated with this role before proceeding.This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.Responsibilities:
Perform Logic Equivalence Check (LEC) to ensure functional consistency between RTL and gate-level netlists.Work closely with front-end design teams to understand design specifications and constraints.Debug and resolve equivalence check issues, including formal verification failures and synthesis mismatches.Provide feedback and recommendations to improve design flows and methodologies for LEC.Document logical equivalence verification processes, methodologies, and results.Perform physical design tasks including synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning, and power optimization.Utilize industry-standard EDA tools for synthesis, LEC, PnR, and timing closure tasks.Experience & Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.5+ years of experience in physical design and verification, with a focus on LEC.Strong understanding of digital design principles, RTL coding, and synthesis.Hands-on experience with synthesis, block and chip level implementation with industry-standard PnR flows and tools.Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.Solid knowledge of scripting languages (e.g., Python, Tcl, Perl) for automation tasks.Excellent problem-solving skills and attention to detail.Strong communication and teamwork skills.
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