Cisco Systems, Inc.
Analog/mixed-signal IC Design - Technical Lead - Acacia
Cisco Systems, Inc., San Jose, California, United States, 95199
Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.
What you'll do:As a member of the Mixed Signal Design team, you will be a key member of a small, dynamic IC Design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products.You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production.You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.
Who you'll work with:You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP design, system design, package design, and module design.Acacia takes pride in providing and fostering a collaborative environment in order to ensure success and personal growth.
Who you are:You are enthusiastic about developing high speed AMS circuits and best-in-class products that push the boundaries of what is possible. You are detail oriented, high energy and the drive to get things done and solve difficult problems.You are capable to figure things out by yourself, but you also participate in our friendly and team-oriented collaboration approach, which means you enjoy learning from your colleagues and letting them learn from you.You are not shy to always point out how we can be more effective as a team, and you are open to similar suggestions by your team members.Your great personal and communication skills allow effortless collaboration within and across teams and to steer the development in a positive direction.
Minimum qualifications:BSEE degree with 8+ years of experience, or equivalent, an MS degree with 6+ years of experience, or equivalent, or a PhD with 3+ years of experience, or equivalent.Design, simulation and measurement of high speed ICs in at least 3 areas below:High Speed Serial Links utilizing serializers, deserializers, and data converters.Voltage RegulatorsHigh Performance Output DriversHigh Performance Phase Locked LoopsEfficient clock Transmission/propagationOpamps and Programmable Gain AmplifiersEqualization techniques
Preferred qualifications:Direct experience with electrical transceiver applications including backplane and cable communicationsExperience with FinFET technologyHigh-frequency layout experience a plus: Passive component design: inductors, transformers, transmission-lines, etc.Floorplanning (power/ground, digital/analog signal routing, etc.)Custom transistor layout
Design for manufacturability:Characterization over PVT (monte-carlo analysis)Electromigration analysis (using Totem, or equivalent)Power and IR drop analysis
Laboratory Validation:Solid ESD laboratory practices and methodologyConstruction of test setup to test specific circuitry
Software Experience:Experience in the use of high frequency test equipment (BERT, jitter analyzers, VNA/PNA, etc.)Cadence (virtuoso)Spectre/APS/SpectreXLayout validation tools (Virtuoso or Calibre)Post-layout Extraction (Virtuoso or Calibre)EMXMixed signal simulations in AMSMatlab
Possess a track record of innovation. Publications are a plus.Applications accepted until August 30th, 2024.
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What you'll do:As a member of the Mixed Signal Design team, you will be a key member of a small, dynamic IC Design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products.You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production.You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.
Who you'll work with:You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP design, system design, package design, and module design.Acacia takes pride in providing and fostering a collaborative environment in order to ensure success and personal growth.
Who you are:You are enthusiastic about developing high speed AMS circuits and best-in-class products that push the boundaries of what is possible. You are detail oriented, high energy and the drive to get things done and solve difficult problems.You are capable to figure things out by yourself, but you also participate in our friendly and team-oriented collaboration approach, which means you enjoy learning from your colleagues and letting them learn from you.You are not shy to always point out how we can be more effective as a team, and you are open to similar suggestions by your team members.Your great personal and communication skills allow effortless collaboration within and across teams and to steer the development in a positive direction.
Minimum qualifications:BSEE degree with 8+ years of experience, or equivalent, an MS degree with 6+ years of experience, or equivalent, or a PhD with 3+ years of experience, or equivalent.Design, simulation and measurement of high speed ICs in at least 3 areas below:High Speed Serial Links utilizing serializers, deserializers, and data converters.Voltage RegulatorsHigh Performance Output DriversHigh Performance Phase Locked LoopsEfficient clock Transmission/propagationOpamps and Programmable Gain AmplifiersEqualization techniques
Preferred qualifications:Direct experience with electrical transceiver applications including backplane and cable communicationsExperience with FinFET technologyHigh-frequency layout experience a plus: Passive component design: inductors, transformers, transmission-lines, etc.Floorplanning (power/ground, digital/analog signal routing, etc.)Custom transistor layout
Design for manufacturability:Characterization over PVT (monte-carlo analysis)Electromigration analysis (using Totem, or equivalent)Power and IR drop analysis
Laboratory Validation:Solid ESD laboratory practices and methodologyConstruction of test setup to test specific circuitry
Software Experience:Experience in the use of high frequency test equipment (BERT, jitter analyzers, VNA/PNA, etc.)Cadence (virtuoso)Spectre/APS/SpectreXLayout validation tools (Virtuoso or Calibre)Post-layout Extraction (Virtuoso or Calibre)EMXMixed signal simulations in AMSMatlab
Possess a track record of innovation. Publications are a plus.Applications accepted until August 30th, 2024.
#J-18808-Ljbffr