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HCLTech

Physical Design (STA)

HCLTech, Austin, Texas, United States,


Job Title: STA EngineerLocation:

Austin, TX (Onsite)Salary Range:

$70-80/hr on W2Job Type:

Full-timeCompany Overview:HCL Technologies

is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. Our technology products and services are built on four decades of innovation, with a world-renowned management philosophy, a strong culture of invention and risk-taking, and a relentless focus on customer relationships. HCL also takes pride in its many diversity, social responsibility, sustainability, and education initiatives. Through its worldwide network of R&D facilities and co-innovation labs, global delivery capabilities, and over 211,000 ‘Ideapreneurs’ across 52 countries, HCL delivers holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 of the Global 2000.Enterprises across industries stand at an inflection point today. In order to thrive in the digital age, technologies such as analytics, cloud, IoT, and automation occupy center stage. In order to offer enterprises the maximum benefit of these technologies to further their business objectives, HCL offers an integrated portfolio of products and services through three business units. These are IT and Business Services (ITBS), Engineering and R&D Services (ERS), and Products and Platforms (P&P).

Job DescriptionEnvironmental Technologies group is seeking temporary professional services of a Regulatory Data Analyst to help manage current product and regulatory compliance data and documentation by product, considering current and future key global regulatory requirements. The Regulatory Data Analyst will collaborate closely with regulatory and data analyst personnel to coordinate and integrate data and create key data visualization outputs.Key Requirements6 to 8+ years of hands-on experience in Static Timing analysis flows.Experience in Multi-mode/Multi-corner runs.Constraints development and management of multi partition design and top levelChip Level IO timing closureExperience in FUNC/DFT timing closureExperience in analysis of timing paths to identify key issues.Timing Convergence ( Both Inter/Intra block Level)Understanding of noise, cross-talk, OCV effects, margins, and constraints.Experience in timing and power ECO techniques and implementationAutomation Skills using scripting languages like TCL/PERL/Python/SHELLTools - Primetime/TempusEducation and ExperienceA BS in an Electrical Engineering or related discipline is required, A MS degree is highly preferred. with 5+ years of relevant industry experience.Benefits:Health Insurance:

Comprehensive medical, dental, and vision insurance.Retirement Plan:

401(k) with company match.Paid Time Off:

Generous PTO policy including vacation, sick leave, and holidays.