Amazon
Physical Design Expert
Amazon, Cupertino, California, United States, 95014
AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.
Make sure to read the full description below, and please apply immediately if you are confident you meet all the requirements.Annapurna Labs is a semiconductor company established by veterans of the industry and is now part of Amazon Web Services (AWS). We develop innovative products, manufactured on cutting edge technologies. We offer a dynamic, open, teamwork environment operating at a rapid pace.Job Description: Exciting opportunity to join Amazon in developing its next generation products for the cloud market. We are looking for talented people to join us, as leaders in our excellent Physical Design team, adopting super advanced process nodes, mentoring team members, and further developing our implementation methodologies.Key Job Responsibilities
Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.Being actively engaged in design-backend convergence aspects and defining timing constraints.Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.Engaged in defining implementation and signoff methodologies.Minimum Requirements
8+ years of experienceUnderstanding the entire place and route flow (“RTL to GDS”)Very deep understanding of timingProcess and technology orientedLeadership and mentoring skillsExperience in advanced nodes technologiesFull-chip experience (floor plan, layout, timing)Previous experience in high-speed designs, multi-voltage (low power) designs
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Make sure to read the full description below, and please apply immediately if you are confident you meet all the requirements.Annapurna Labs is a semiconductor company established by veterans of the industry and is now part of Amazon Web Services (AWS). We develop innovative products, manufactured on cutting edge technologies. We offer a dynamic, open, teamwork environment operating at a rapid pace.Job Description: Exciting opportunity to join Amazon in developing its next generation products for the cloud market. We are looking for talented people to join us, as leaders in our excellent Physical Design team, adopting super advanced process nodes, mentoring team members, and further developing our implementation methodologies.Key Job Responsibilities
Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.Being actively engaged in design-backend convergence aspects and defining timing constraints.Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.Engaged in defining implementation and signoff methodologies.Minimum Requirements
8+ years of experienceUnderstanding the entire place and route flow (“RTL to GDS”)Very deep understanding of timingProcess and technology orientedLeadership and mentoring skillsExperience in advanced nodes technologiesFull-chip experience (floor plan, layout, timing)Previous experience in high-speed designs, multi-voltage (low power) designs
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