ESR Healthcare
Asic design engnr video graphics
ESR Healthcare, San Jose, California, United States, 95123
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For a complete understanding of this opportunity, and what will be required to be a successful applicant, read on.Experience level:
Mid-senior
Experience required:
8 Years
Education level:
Bachelor’s degree
Job function:
Information Technology
Industry:
Information Technology and Services
Compensation:
View salary
Total position:
5
Relocation assistance:
Yes
Visa:
Only US citizens and Greencard holders
You will be part of the IC design team, creating and bringing to market GEO’s next generation automotive camera video/vision processors. Located in the Toronto office, you will have the following responsibilities:
Architect, design and verify key processing blocks of automotive camera video/vision processors.
Work closely with the algorithm team to enhance efficiency and performance of next generation image processing elements.
Design elements of the SOC processing fabric including CPU, high speed interfaces, interconnect fabric, top level clock and reset structures.
Design of power management structures to achieve the lowest power consumption in multiple operational modes.
Develop block/system level RTL to meet synthesis/physical, DFT and power goals.
Develop block architecture & RTL that will meet the functional safety requirements of the chip.
Collaborate with the physical design team to meet overall physical design targets.
Work with verification team to develop and review block and chip level verification environments and test plans.
Work with the systems and software teams on emulation platforms and lead the bring-up of your designed blocks.
Play a key role in the bring-up of your design elements in the device prototype.
Provide support to the Product Engineering team to meet all validation, characterization and qualification goals for the product.
QUALIFICATIONS
BSEE +
8 years of industry experience in digital design.
A history of working with video/graphics processing.
Development history with neural network accelerators a plus.
Experience in RTL design with Verilog/System Verilog.
Understanding of standard IC design methodology with simulation, synthesis, timing closure and DFT.
Familiarity with design verification and the ability to independently develop block level test suites.
Strong programming skills in C and scripting languages such as Python.
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For a complete understanding of this opportunity, and what will be required to be a successful applicant, read on.Experience level:
Mid-senior
Experience required:
8 Years
Education level:
Bachelor’s degree
Job function:
Information Technology
Industry:
Information Technology and Services
Compensation:
View salary
Total position:
5
Relocation assistance:
Yes
Visa:
Only US citizens and Greencard holders
You will be part of the IC design team, creating and bringing to market GEO’s next generation automotive camera video/vision processors. Located in the Toronto office, you will have the following responsibilities:
Architect, design and verify key processing blocks of automotive camera video/vision processors.
Work closely with the algorithm team to enhance efficiency and performance of next generation image processing elements.
Design elements of the SOC processing fabric including CPU, high speed interfaces, interconnect fabric, top level clock and reset structures.
Design of power management structures to achieve the lowest power consumption in multiple operational modes.
Develop block/system level RTL to meet synthesis/physical, DFT and power goals.
Develop block architecture & RTL that will meet the functional safety requirements of the chip.
Collaborate with the physical design team to meet overall physical design targets.
Work with verification team to develop and review block and chip level verification environments and test plans.
Work with the systems and software teams on emulation platforms and lead the bring-up of your designed blocks.
Play a key role in the bring-up of your design elements in the device prototype.
Provide support to the Product Engineering team to meet all validation, characterization and qualification goals for the product.
QUALIFICATIONS
BSEE +
8 years of industry experience in digital design.
A history of working with video/graphics processing.
Development history with neural network accelerators a plus.
Experience in RTL design with Verilog/System Verilog.
Understanding of standard IC design methodology with simulation, synthesis, timing closure and DFT.
Familiarity with design verification and the ability to independently develop block level test suites.
Strong programming skills in C and scripting languages such as Python.
#J-18808-Ljbffr