Synopsys Inc
ASIC Digital Design Manager - 47174BR
Synopsys Inc, Mountain View, California, us, 94039
Senior Manager ASIC Digital Design – Sunnyvale
Do you have the skills to fill this role Read the complete details below, and make your application today.At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP Subsystems business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.We’re looking for a Senior ASIC Digital Design Manager to join Synopsys Solutions Group, Digital IP Subsystems Team in Sunnyvale, CA. Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs.In this role:As a Subsystems Manager, you will be detail-oriented with a track record of execution excellence. You should possess strong communication skills, including customer interface, and be hands-on when necessary. You will lead a team of up to 5 to 8 members.You will be responsible for hands-on RTL Design, Verification, Architecting & Integrating the Subsystems, and signing off on the front-end implementation flows. You will work with Design and Verification teams, driving the life-cycle of the Subsystems from requirement to release phases.Requirements & Skills:Experience in managing remote teams independently for a minimum of 5 to 10 years.As a Techno-Manager, knowledge of one or more protocols: AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.Programming skills such as System Verilog, TCL, Perl, or Python.The ability to motivate the team and drive innovation.The ability to extract detailed requirements from high-level specifications, foresee the team's work, track progress, and drive towards clean-closure.Good communication skills.As a Manager, this position will require you and your team to:Understand the requirements and architect the Subsystems based on the requirements.Integrate the RTL and drive the design tasks to complete the Subsystem.Sign-off on the front-end implementation flows like synthesis timing closure using Fusion Compiler, SpyGlass CDC/RDC checks, low power architecture, Formality, and others.Drive towards verification closure. Understand the Subsystem requirements/specification and author the Verification Plan. Develop the SV UVM Test Environment.Drive the life-cycle of the Subsystems through various phases, from requirements to delivery.Key Qualifications for This Techno-Managerial Role:Bachelor's or Master’s degree in electronics with overall experience of 10+ years.Techno-managerial experience of 5 to 10 years.Hands-on/lead experience in Subsystems/SoC Design, Architecture, and Implementation.Experience with Verilog/System Verilog coding and simulation tools.Experience of implementation flows, namely: synthesis flow, lint, CDC, low power, and others.Hands-on/lead experience in Subsystem Verification.Experience in developing and implementing test plans, extracting verification metrics, developing BFMs, and similar verification components.The base salary range across the U.S. for this role is between $111,000.00-$194,000.00. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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Do you have the skills to fill this role Read the complete details below, and make your application today.At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP Subsystems business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.We’re looking for a Senior ASIC Digital Design Manager to join Synopsys Solutions Group, Digital IP Subsystems Team in Sunnyvale, CA. Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs.In this role:As a Subsystems Manager, you will be detail-oriented with a track record of execution excellence. You should possess strong communication skills, including customer interface, and be hands-on when necessary. You will lead a team of up to 5 to 8 members.You will be responsible for hands-on RTL Design, Verification, Architecting & Integrating the Subsystems, and signing off on the front-end implementation flows. You will work with Design and Verification teams, driving the life-cycle of the Subsystems from requirement to release phases.Requirements & Skills:Experience in managing remote teams independently for a minimum of 5 to 10 years.As a Techno-Manager, knowledge of one or more protocols: AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.Programming skills such as System Verilog, TCL, Perl, or Python.The ability to motivate the team and drive innovation.The ability to extract detailed requirements from high-level specifications, foresee the team's work, track progress, and drive towards clean-closure.Good communication skills.As a Manager, this position will require you and your team to:Understand the requirements and architect the Subsystems based on the requirements.Integrate the RTL and drive the design tasks to complete the Subsystem.Sign-off on the front-end implementation flows like synthesis timing closure using Fusion Compiler, SpyGlass CDC/RDC checks, low power architecture, Formality, and others.Drive towards verification closure. Understand the Subsystem requirements/specification and author the Verification Plan. Develop the SV UVM Test Environment.Drive the life-cycle of the Subsystems through various phases, from requirements to delivery.Key Qualifications for This Techno-Managerial Role:Bachelor's or Master’s degree in electronics with overall experience of 10+ years.Techno-managerial experience of 5 to 10 years.Hands-on/lead experience in Subsystems/SoC Design, Architecture, and Implementation.Experience with Verilog/System Verilog coding and simulation tools.Experience of implementation flows, namely: synthesis flow, lint, CDC, low power, and others.Hands-on/lead experience in Subsystem Verification.Experience in developing and implementing test plans, extracting verification metrics, developing BFMs, and similar verification components.The base salary range across the U.S. for this role is between $111,000.00-$194,000.00. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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