Tenstorrent
Staff, Physical Design Engineeer - LEC
Tenstorrent, Austin, Texas, us, 78716
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Be a part of a dynamic Physical Design team working on high-performance designs going into industry leading CPU and AI/ML architecture. This role involves performing Logic Equivalence Checks (LEC) to ensure functional consistency between RTL and gate-level netlists, along with debugging and resolving equivalence issues. The candidate will work closely with front-end design teams and engage in physical design tasks such as synthesis, PnR, and timing closure. A strong background in digital design, RTL coding, and experience with industry-standard EDA tools is essential.
This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Perform Logic Equivalence Check (LEC) to ensure functional consistency between RTL and gate-level netlists.Work closely with front-end design teams to understand design specifications and constraints.Debug and resolve equivalence check issues, including formal verification failures and synthesis mismatches.Provide feedback and recommendations to improve design flows and methodologies for LEC.Document logical equivalence verification processes, methodologies, and results.Perform physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimizationUtilize industry-standard EDA tools Synthesis, LEC, PnR, timing closure tasks.Experience & Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.5+ years of experience in physical design and verification, with a focus on LEC.Strong understanding of digital design principles, RTL coding, and synthesis.Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools.Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.Solid knowledge of scripting languages (e.g., Python, Tcl, Perl) for automation tasks.Excellent problem-solving skills and attention to detail.Strong communication and teamwork skills.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.
Be a part of a dynamic Physical Design team working on high-performance designs going into industry leading CPU and AI/ML architecture. This role involves performing Logic Equivalence Checks (LEC) to ensure functional consistency between RTL and gate-level netlists, along with debugging and resolving equivalence issues. The candidate will work closely with front-end design teams and engage in physical design tasks such as synthesis, PnR, and timing closure. A strong background in digital design, RTL coding, and experience with industry-standard EDA tools is essential.
This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Perform Logic Equivalence Check (LEC) to ensure functional consistency between RTL and gate-level netlists.Work closely with front-end design teams to understand design specifications and constraints.Debug and resolve equivalence check issues, including formal verification failures and synthesis mismatches.Provide feedback and recommendations to improve design flows and methodologies for LEC.Document logical equivalence verification processes, methodologies, and results.Perform physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimizationUtilize industry-standard EDA tools Synthesis, LEC, PnR, timing closure tasks.Experience & Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.5+ years of experience in physical design and verification, with a focus on LEC.Strong understanding of digital design principles, RTL coding, and synthesis.Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools.Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.Solid knowledge of scripting languages (e.g., Python, Tcl, Perl) for automation tasks.Excellent problem-solving skills and attention to detail.Strong communication and teamwork skills.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.