System Verilog / UVM Design Verification Job at Apptad Inc in Dallas

Role: System Verilog / UVM Design Verification
Work Location: Dallas, TX (Day1 Onsite)
Position Type: 12+ Months

Job Description
Responsible for writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for SoCs/Subsystems
Create System Verilog / UVM verification environment.
Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.
Run regressions, debug test failures and file bug report as needed.
Provide verification report as needed to show all implemented tests passing on the RTL.

Required Skills / Experience
Candidate must have minimum 5 years of experience in functional verification
Candidate must have strong knowledge of System Verilog and in UVM methodology
Candidate must have knowledge of AXI, AHB protocol