Senior Staff Engineer, Electrical Design Job at CV Library in San Jose

Job Description Responsibilities: Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit. Contribute within a highly experienced team of engineers with extensive cross-functional skill sets. Employ clocking controls, FSM design, low power techniques, and high-speed design concepts. Participate in design, architecture, and verification reviews. Cover digital backend design from synthesis, static timing, and logic equivalent checking. Create documentation targeting design, verification, and test groups. Assist with new feature proposal, definition, documentation, and implementation. Mentor and help train junior and New College Grad engineers. #J-18808-Ljbffr