Cisco Systems, Inc.
ASIC Physical Design Technical Leader
Cisco Systems, Inc., San Jose, California, United States, 95199
The application window is expected to close on: 2/20/25
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact You'll be joining our Physical Design team at
Cisco Silicon One
group, which is responsible for the entire development process of RTL to GDS, leading development of high quality VLSI designs. Responsibilities include: Fullchip
Floorplan and Partition/Pin assignment. Fullchip
Clock Planning (Experience with both H-Tree and Clock Mesh architectures). Interface
with Fullchip STA team on timing constraints. Power
Planning and Robust Power Grid planning for lower technology nodes. Fullchip
Physical Verification.
Minimum Qualifications Bachelor's
degree in Electrical Engineering or equivalent similar experience. 8+
years of experience in Physical Design. Experience
working on Fullchip activities. Experience
with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process
technologies. Experience
working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or
Calibre. Preferred Qualifications Exposure
to static timing analysis and concepts, defining timing constraints and
exceptions, corners/voltage definitions. Experience
in Full-chip floor-planning and power grid planning. Experience
with custom clock (H-Tree or Mesh) at chip level Experience
with Python, TCL, Perl programming. WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!
Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact You'll be joining our Physical Design team at
Cisco Silicon One
group, which is responsible for the entire development process of RTL to GDS, leading development of high quality VLSI designs. Responsibilities include: Fullchip
Floorplan and Partition/Pin assignment. Fullchip
Clock Planning (Experience with both H-Tree and Clock Mesh architectures). Interface
with Fullchip STA team on timing constraints. Power
Planning and Robust Power Grid planning for lower technology nodes. Fullchip
Physical Verification.
Minimum Qualifications Bachelor's
degree in Electrical Engineering or equivalent similar experience. 8+
years of experience in Physical Design. Experience
working on Fullchip activities. Experience
with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process
technologies. Experience
working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or
Calibre. Preferred Qualifications Exposure
to static timing analysis and concepts, defining timing constraints and
exceptions, corners/voltage definitions. Experience
in Full-chip floor-planning and power grid planning. Experience
with custom clock (H-Tree or Mesh) at chip level Experience
with Python, TCL, Perl programming. WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!