Rose International
NEW JOB OPENING MASK LAYOUT DESIGNER IN CUPERTINO, CA, USA!
Rose International, San Francisco, California, United States, 94199
Job Description
Schedule Note: Candidates must be local to San Diego or the Bay Area and will follow a hybrid work schedule.
Minimum Qualifications: • BS and 5+ years of relevant industry experience. • FinFet experience
Preferred Qualifications: • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. • Solid understanding of RC delay, electromigration, and coupling. • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc. • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred) • Knowledge of CADENCE layout tools. • Excellent communication skills and able to work with cross-functional teams. • Scripting skills in PERL or SKILL are a plus but not required.
Summary: Our teams are responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will work closely with the design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Client's state-of-the-art designs and getting them into hundreds of millions of products.
As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next generation of wireless technologies into high-volume production in advanced CMOS technology nodes. Responsibilities include: - • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. • Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. • Co-work with designers on block level floorplanning. • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
**Only those lawfully authorized to work in the designated country associated with the position will be considered.**
**Please note that all Position start dates and duration are estimates and may be reduced or lengthened based upon a client's business needs and requirements.**
Benefits: For information and details on employment benefits offered with this position, please visit here . Should you have any questions/concerns, please contact our HR Department via our secure website .
California Pay Equity: For information and details on pay equity laws in California, please visit the State of California Department of Industrial Relations' website here .
Rose International is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender (expression or identity), national origin, arrest and conviction records, disability, veteran status or any other characteristic protected by law. Positions located in San Francisco and Los Angeles, California will be administered in accordance with their respective Fair Chance Ordinances.
If you need assistance in completing this application, or during any phase of the application, interview, hiring, or employment process, whether due to a disability or otherwise, please contact our HR Department .
Rose International has an official agreement (ID #132522), effective June 30, 2008, with the U.S. Department of Homeland Security, U.S. Citizenship and Immigration Services, Employment Verification Program (E-Verify). (Posting required by OCGA 13/10-91.).
Minimum Qualifications: • BS and 5+ years of relevant industry experience. • FinFet experience
Preferred Qualifications: • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. • Solid understanding of RC delay, electromigration, and coupling. • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc. • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred) • Knowledge of CADENCE layout tools. • Excellent communication skills and able to work with cross-functional teams. • Scripting skills in PERL or SKILL are a plus but not required.
Summary: Our teams are responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will work closely with the design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Client's state-of-the-art designs and getting them into hundreds of millions of products.
As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next generation of wireless technologies into high-volume production in advanced CMOS technology nodes. Responsibilities include: - • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. • Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. • Co-work with designers on block level floorplanning. • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
**Only those lawfully authorized to work in the designated country associated with the position will be considered.**
**Please note that all Position start dates and duration are estimates and may be reduced or lengthened based upon a client's business needs and requirements.**
Benefits: For information and details on employment benefits offered with this position, please visit here . Should you have any questions/concerns, please contact our HR Department via our secure website .
California Pay Equity: For information and details on pay equity laws in California, please visit the State of California Department of Industrial Relations' website here .
Rose International is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender (expression or identity), national origin, arrest and conviction records, disability, veteran status or any other characteristic protected by law. Positions located in San Francisco and Los Angeles, California will be administered in accordance with their respective Fair Chance Ordinances.
If you need assistance in completing this application, or during any phase of the application, interview, hiring, or employment process, whether due to a disability or otherwise, please contact our HR Department .
Rose International has an official agreement (ID #132522), effective June 30, 2008, with the U.S. Department of Homeland Security, U.S. Citizenship and Immigration Services, Employment Verification Program (E-Verify). (Posting required by OCGA 13/10-91.).