TPI Global Solutions
ASIC/RTL Design Job at TPI Global Solutions in San Francisco Bay Area
TPI Global Solutions, San Francisco Bay Area, United States
Title: ASIC/RTL Design Engineer
Location: San Jose California - Onsite
Interviews: 2 Interviews (Online).
Rate: $78.57/Hour
Top skills:
RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime).
Job Duties:
- The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IP's.
- Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.
- Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
Experience and Education:
- SoC Design;
- Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.
- Experience with front end quality checks such as Lint, CDC, RDC. Running, Debugging, Reporting, Driving Cleanup.
- Working knowledge of ARM cores and other I/O standard interfaces.
- Roughly 10 years experience, but less is acceptable.
- Bachelors in electrical engineering or computer engineering is preferred