ASIC Design Manager
TenaFe - Campbell, California, us, 95011![TenaFe](/api/image?src=https%3A%2F%2Fgeneral-board-default.s3.us-east-2.amazonaws.com%2Fpublic%2Fimages%2Fdesk-360x180.webp&w=640&q=75&f=webp)
Work at TenaFe
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Overview
Degree Required: BS or Higher, MS or higher preferred
Academic Discipline (s): EE, CS or related fields, or BS with 12+ years work experience or MS with 10+ years work experience
Job Description:
As an ASIC Design Manager for the SSD ASIC Design Team, you are expected to play a key role in developing cutting edge SSD controller products and you will experience a different and exciting journey at TenaFe.
Job Duties/Responsibilities:
* RTL Coding, including block design, top level design, Lower power design, and CPF/UPF design* Verify design and debug in RTL-level, gate-level and PG gate level* Simulations, design constraints, coding style checking, cross clock domain checking, synthesis and timing closures* Bug analysis and fixing, formal check.* Area, Power, FIT estimation/measure, DFT related, and ATE support* Deliver design/verification/application documents/SPEC* Work closely with the Algorithm Engineer to develop and debug new IP/products* Work closely with the Verification/System/Firmware Engineer to verify/validate new IP/products* Work closely with the Architecture and Firmware Teams to define the function of blocks* Work closely with the Architecture and Firmware Teams to settle down SoC level, subsystem, block level FW/HW partition, and architecture* Be able to learn new knowledge* Ability to provide team culture and efficiency management, team output quality management, project planning and schedule management.* Ability to communicate across teams, coordinate tasks, resource and schedule.
Required Qualifications:
* Experience in Verilog code design and verification* Experience in Unix/Linux OS, and scripting language like Perl* Experience in ASIC frontend flow and related tools (synthesis, formal, STA and DFT tools)* Experience in Lower power design and verification with UPF/CPF* Good understanding of circuit design and timing constraints for synthesis/STA* Familiar with C, UVM* Familiar with formal check, DFT related, ATE related* Strong problem solving ability* Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form* A high level of self-motivation, the ability to be a self-starter with a good attitude and be highly responsible* Good written, verbal and presentation communication skills* Ability to work in a team environment* Team management/Lead experience* BS with 12+ years work experience or MS with 10+ years work experience
Knowledge and skill preferred, but not required:
* Demonstrate SSD controller design experience* Complicated SOC design experience* Expertise on PCIe and NVMe* Expertise on DDR and NAND flash