Manager - Design Verification Bangalore, India
Tbwa Chiat/Day Inc - California, Missouri, United States, 65018![Tbwa Chiat/Day Inc](/api/image?src=https%3A%2F%2Fgeneral-board-default.s3.us-east-2.amazonaws.com%2Fpublic%2Fimages%2Fdesk-360x180.webp&w=640&q=75&f=webp)
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Overview
Design Verification (DV) Manager
to join a growing start-up semiconductor development organization and to help drive excellence in our 5G ORAN products.Key ResponsibilitiesManage 10-12 DV & design engineers for technical leadership and mentoring team members for team building.Work as the primary interface to US design/verification team members and management.Track verification progress, identify and close verification gaps to show progress towards tape-out.Provide an executive summary for the verification status on each sub-system.Full-chip functional verification of 5G Digital Radio SOC.Develop, review and execute SOC verification plans on internal and 3rd party IPs.Architect verification framework for mixed-signal SOC verification.Verify full chip SoC using UVM - Directed/Constrained-Random.Verify internal and 3rd party IP blocks with functional vector, VIP and UVM.Collaborate with cross-functional teams (System, Emulation, FW) for silicon tapeout and product solution development.Explore and propose advanced verification methodologies - UVM, FPGA prototyping, emulation.Minimum QualificationsTech or B.Tech degree in Electrical or Computer Engineering or equivalent.15+ years of successfully executing and/or managing multiple IP, SOC Verification projects.Have successfully led verification efforts at IP and/or SOC level for multiple projects.Extensive experience in developing UVM-based SV test-benches - Directed/Constrained-Random.Deep understanding and knowledge of verification methodologies, flows and quality.Prior work experience with complex coverage-driven random constraint UVM.Strong experience with digital logic design, and logic verification methodology.Hands-on experience with CNDS simulation and verification tools (Xcelium, vManager).Hands-on experience in 3rd party IP verification using VIPs from CNDS/SNPS with front/back-door loading/configuration.Hands-on experience in multi-core ARM CPUs & AXI/AHB/API bus system verification.Hands-on experience developing verification collateral in System Verilog and UVM.Familiar with version control software like Git, Subversion.Familiar with gate-level simulation.Familiar with boot ROM simulations.Familiar with MATLAB simulations.Experience on FPGA emulation.Good knowledge of programming languages such as C, VHDL, System-Verilog and scripting languages like TCL and Python.Preferred SkillsKnowledge of ARM and Wireless signal-processing design is highly desirable.UVM proficiency is required.Strong communication skills both written and verbal.Ambitious and goal-oriented.Collaborate effectively in a dynamic team environment.
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