Design 2 Build
Director Physical design SiFive $208.7k - $287.4k/year ⋅ Santa Clara, CA
Design 2 Build, Santa Clara, California, us, 95053
10+ years Santa Clara, CA $208.7k - $287.4k/year Full-time Hybrid 6 days agoDirector Physical design SiFive 10+ years Santa Clara, CA $208.7k - $287.4k/year Full-time Hybrid 6 days ago About the role About SiFive
Make sure to read the full description below, and please apply immediately if you are confident you meet all the requirements.As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.Are you ready?To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.Job Description:Responsibilities
Implementing and optimizing our broad portfolio of RISC-V IPs from RTL to GDSII. Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level. Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs. Contributing to physical implementation flow development to drive best-in-class automation and PPA. Debug and resolve physical design issues of SiFive's RISC-V IPs for pre- and post-sales customers Improve and enhance the customer experience of physical design implementation using foundation flows of major EDA vendors Generate high quality PPA (Power, Performance and Area) collaterals for broad portfolio of SiFive CPU IP and participate in PPA benchmarking for customer designs Work closely with the RM (Release Management) team to ensure the physical design quality of the different designs delivered to customers and drive necessary automation around it Automate the generation, data extraction/analysis and management of PPA collaterals Collaborate with physical design flow development teams to drive best-in-class automation and PPA Work closely with EDA vendors to develop out of box solutionsRequirements10+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes is strongly preferred Expertise in aggressive PPA optimization through physical design techniques Understanding of logic design, CPU subsystem, FUSA architecture is a strong plus Working experience on a customer-facing role is strongly preferred Experience in one or more aspects of PD such as sign-off (PnR, timing), physical verification, IR/EM is strongly preferred Expertise on creating large scale automation to support variety of customers and internal teams is strongly preferred Attention to detail and a focus on high-quality deliverable Ability to work well with others and a belief that engineering is a team sport.-Compensation Range:$208,725-$287,375Additional Information:This position requires a successful background and reference checks and satisfactory proof of your right to work inUnited States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document . Skills INFORMATION TECHNOLOGY DESIGN ART/CREATIVE SEMICONDUCTOR MANUFACTURING Physical design implementation RISC-V IPs optimization Performance, power, and area (PPA) optimization Microarchitecture and RTL optimization Physical implementation flow development Debugging physical design issues Customer-facing role experience Automation in physical design Logic design and CPU subsystem understanding Large scale automation development#J-18808-Ljbffr
Make sure to read the full description below, and please apply immediately if you are confident you meet all the requirements.As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.Are you ready?To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.Job Description:Responsibilities
Implementing and optimizing our broad portfolio of RISC-V IPs from RTL to GDSII. Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level. Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs. Contributing to physical implementation flow development to drive best-in-class automation and PPA. Debug and resolve physical design issues of SiFive's RISC-V IPs for pre- and post-sales customers Improve and enhance the customer experience of physical design implementation using foundation flows of major EDA vendors Generate high quality PPA (Power, Performance and Area) collaterals for broad portfolio of SiFive CPU IP and participate in PPA benchmarking for customer designs Work closely with the RM (Release Management) team to ensure the physical design quality of the different designs delivered to customers and drive necessary automation around it Automate the generation, data extraction/analysis and management of PPA collaterals Collaborate with physical design flow development teams to drive best-in-class automation and PPA Work closely with EDA vendors to develop out of box solutionsRequirements10+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes is strongly preferred Expertise in aggressive PPA optimization through physical design techniques Understanding of logic design, CPU subsystem, FUSA architecture is a strong plus Working experience on a customer-facing role is strongly preferred Experience in one or more aspects of PD such as sign-off (PnR, timing), physical verification, IR/EM is strongly preferred Expertise on creating large scale automation to support variety of customers and internal teams is strongly preferred Attention to detail and a focus on high-quality deliverable Ability to work well with others and a belief that engineering is a team sport.-Compensation Range:$208,725-$287,375Additional Information:This position requires a successful background and reference checks and satisfactory proof of your right to work inUnited States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document . Skills INFORMATION TECHNOLOGY DESIGN ART/CREATIVE SEMICONDUCTOR MANUFACTURING Physical design implementation RISC-V IPs optimization Performance, power, and area (PPA) optimization Microarchitecture and RTL optimization Physical implementation flow development Debugging physical design issues Customer-facing role experience Automation in physical design Logic design and CPU subsystem understanding Large scale automation development#J-18808-Ljbffr