Oceanside Physical Therapy
Director Physical design
Oceanside Physical Therapy, Santa Clara, California, us, 95053
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
Hit Apply below to send your application for consideration Ensure that your CV is up to date, and that you have read the job specs first.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.Are you ready?To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our
website
and
Glassdoor
pages.Job Description:ResponsibilitiesImplementing and optimizing our broad portfolio of RISC-V IPs from RTL to GDSII.Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level.Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs.Contributing to physical implementation flow development to drive best-in-class automation and PPA.Debug and resolve physical design issues of SiFive's RISC-V IPs for pre- and post-sales customersImprove and enhance the customer experience of physical design implementation using foundation flows of major EDA vendorsGenerate high quality PPA (Power, Performance and Area) collaterals for broad portfolio of SiFive CPU IP and participate in PPA benchmarking for customer designsWork closely with the RM (Release Management) team to ensure the physical design quality of the different designs delivered to customers and drive necessary automation around itAutomate the generation, data extraction/analysis and management of PPA collateralsCollaborate with physical design flow development teams to drive best-in-class automation and PPAWork closely with EDA vendors to develop out of box solutionsRequirements10+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes is strongly preferredExpertise in aggressive PPA optimization through physical design techniquesUnderstanding of logic design, CPU subsystem, FUSA architecture is a strong plusWorking experience on a customer-facing role is strongly preferredExperience in one or more aspects of PD such as sign-off (PnR, timing), physical verification, IR/EM is strongly preferredExpertise on creating large scale automation to support variety of customers and internal teams is strongly preferredAttention to detail and a focus on high-quality deliverableAbility to work well with others and a belief that engineering is a team sport.Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.Base Pay Range$217,800.00-$266,200.00
About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.Are you ready?To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our
website
and
Glassdoor
pages.Job Description:ResponsibilitiesImplementing and optimizing our broad portfolio of RISC-V IPs from RTL to GDSII.
Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level.
Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs.
Contributing to physical implementation flow development to drive best-in-class automation and PPA.
Debug and resolve physical design issues of SiFive's RISC-V IPs for pre- and post-sales customers
Improve and enhance the customer experience of physical design implementation using foundation flows of major EDA vendors
Generate high quality PPA (Power, Performance and Area) collaterals for broad portfolio of SiFive CPU IP and participate in PPA benchmarking for customer designs
Work closely with the RM (Release Management) team to ensure the physical design quality of the different designs delivered to customers and drive necessary automation around it
Automate the generation, data extraction/analysis and management of PPA collaterals
Collaborate with physical design flow development teams to drive best-in-class automation and PPA
Work closely with EDA vendors to develop out of box solutions
Requirements10+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes is strongly preferred
Expertise in aggressive PPA optimization through physical design techniques
Understanding of logic design, CPU subsystem, FUSA architecture is a strong plus
Working experience on a customer-facing role is strongly preferred
Experience in one or more aspects of PD such as sign-off (PnR, timing), physical verification, IR/EM is strongly preferred
Expertise on creating large scale automation to support variety of customers and internal teams is strongly preferred
Attention to detail and a focus on high-quality deliverable
Ability to work well with others and a belief that engineering is a team sport.
Pay & BenefitsConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.Base Pay Range$217,800.00-$266,200.00 In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!Additional Information:This position requires a successful background and reference checks and satisfactory proof of your right to work inUnited States of America
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights:
Privacy Policy Document
.
#J-18808-Ljbffr
Hit Apply below to send your application for consideration Ensure that your CV is up to date, and that you have read the job specs first.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.Are you ready?To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our
website
and
Glassdoor
pages.Job Description:ResponsibilitiesImplementing and optimizing our broad portfolio of RISC-V IPs from RTL to GDSII.Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level.Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs.Contributing to physical implementation flow development to drive best-in-class automation and PPA.Debug and resolve physical design issues of SiFive's RISC-V IPs for pre- and post-sales customersImprove and enhance the customer experience of physical design implementation using foundation flows of major EDA vendorsGenerate high quality PPA (Power, Performance and Area) collaterals for broad portfolio of SiFive CPU IP and participate in PPA benchmarking for customer designsWork closely with the RM (Release Management) team to ensure the physical design quality of the different designs delivered to customers and drive necessary automation around itAutomate the generation, data extraction/analysis and management of PPA collateralsCollaborate with physical design flow development teams to drive best-in-class automation and PPAWork closely with EDA vendors to develop out of box solutionsRequirements10+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes is strongly preferredExpertise in aggressive PPA optimization through physical design techniquesUnderstanding of logic design, CPU subsystem, FUSA architecture is a strong plusWorking experience on a customer-facing role is strongly preferredExperience in one or more aspects of PD such as sign-off (PnR, timing), physical verification, IR/EM is strongly preferredExpertise on creating large scale automation to support variety of customers and internal teams is strongly preferredAttention to detail and a focus on high-quality deliverableAbility to work well with others and a belief that engineering is a team sport.Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.Base Pay Range$217,800.00-$266,200.00
About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.Are you ready?To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our
website
and
Glassdoor
pages.Job Description:ResponsibilitiesImplementing and optimizing our broad portfolio of RISC-V IPs from RTL to GDSII.
Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level.
Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs.
Contributing to physical implementation flow development to drive best-in-class automation and PPA.
Debug and resolve physical design issues of SiFive's RISC-V IPs for pre- and post-sales customers
Improve and enhance the customer experience of physical design implementation using foundation flows of major EDA vendors
Generate high quality PPA (Power, Performance and Area) collaterals for broad portfolio of SiFive CPU IP and participate in PPA benchmarking for customer designs
Work closely with the RM (Release Management) team to ensure the physical design quality of the different designs delivered to customers and drive necessary automation around it
Automate the generation, data extraction/analysis and management of PPA collaterals
Collaborate with physical design flow development teams to drive best-in-class automation and PPA
Work closely with EDA vendors to develop out of box solutions
Requirements10+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes is strongly preferred
Expertise in aggressive PPA optimization through physical design techniques
Understanding of logic design, CPU subsystem, FUSA architecture is a strong plus
Working experience on a customer-facing role is strongly preferred
Experience in one or more aspects of PD such as sign-off (PnR, timing), physical verification, IR/EM is strongly preferred
Expertise on creating large scale automation to support variety of customers and internal teams is strongly preferred
Attention to detail and a focus on high-quality deliverable
Ability to work well with others and a belief that engineering is a team sport.
Pay & BenefitsConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.Base Pay Range$217,800.00-$266,200.00 In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!Additional Information:This position requires a successful background and reference checks and satisfactory proof of your right to work inUnited States of America
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights:
Privacy Policy Document
.
#J-18808-Ljbffr