Acceler8 Talent
Senior Physical Design Member of Technical Staff
Acceler8 Talent, Mountain View, California, United States,
Senior Physical Design Member of Technical Staff
Acceler8 Talent is seeking a Senior Design Verification Engineer to join an early-stage AI hardware startup. This pioneering company is focused on developing custom chips for Large Language Models (LLMs), aiming to achieve significantly higher efficiency and performance compared to existing market leaders.Founded by the esteemed engineers who helped develop the industry’s most prominent AI platforms, and have had previous successful exits, this company is exceedingly well funded and is building the task force that will create the future of Generative AI compute.
ResponsibilitiesOwn subsystems of chip-level physical design including: floor-planning, placement, clock insertion, routing, and timing closure analysis.Define and implement critical physical structures, including clock and reset architecture, power delivery network, and interconnect technologies.Optimize design for timing, power, and area utilizing advanced physical design tools and methodologies.Collaborate with the verification team to ensure rigorous formal verification and Logic Equivalence Check (LEC) to validate alignment with functional requirements.Ensure smooth transition from physical design to tape-out by working closely with the back-end team.
RequirementsB.S/M.S in Electrical Engineering or Computer Engineering with 7+ years experienceProven industry experience in the physical implementation of large, high-performance network switching / routing fabrics (Ethernet, Infiniband, HPC)
This position will be hybrid-remote, with 3 days per week on-site from their Mountain View office.
They are looking to get someone started ASAP and will offer compensation consisting of competitive base salary + stock options.
Please apply here or contact jtyler@acceler8talent.com if you’d like to learn more.
Acceler8 Talent is seeking a Senior Design Verification Engineer to join an early-stage AI hardware startup. This pioneering company is focused on developing custom chips for Large Language Models (LLMs), aiming to achieve significantly higher efficiency and performance compared to existing market leaders.Founded by the esteemed engineers who helped develop the industry’s most prominent AI platforms, and have had previous successful exits, this company is exceedingly well funded and is building the task force that will create the future of Generative AI compute.
ResponsibilitiesOwn subsystems of chip-level physical design including: floor-planning, placement, clock insertion, routing, and timing closure analysis.Define and implement critical physical structures, including clock and reset architecture, power delivery network, and interconnect technologies.Optimize design for timing, power, and area utilizing advanced physical design tools and methodologies.Collaborate with the verification team to ensure rigorous formal verification and Logic Equivalence Check (LEC) to validate alignment with functional requirements.Ensure smooth transition from physical design to tape-out by working closely with the back-end team.
RequirementsB.S/M.S in Electrical Engineering or Computer Engineering with 7+ years experienceProven industry experience in the physical implementation of large, high-performance network switching / routing fabrics (Ethernet, Infiniband, HPC)
This position will be hybrid-remote, with 3 days per week on-site from their Mountain View office.
They are looking to get someone started ASAP and will offer compensation consisting of competitive base salary + stock options.
Please apply here or contact jtyler@acceler8talent.com if you’d like to learn more.