GeoLogics Corporation
ASIC Physical Design Lead (2) needed -- Salaried-Hybrid position
GeoLogics Corporation, New York, New York, United States,
2 Sr. ASIC Physical Design Leads needed --- Salaried Position
GeoLogics
is working with a hiring manager at
an innovative Fabless Semiconductor Company
and he is in search of
2
Senior ASIC Physical Design Lead , needed for a hybrid-salaried position.
2 Senior ASIC Physical Design LeadMust be a United States Citizen or Green Card HolderHybrid Position – Orange County/San Diego (3 day’s on/2 day’s off)888-303-3603
Salaried position (DOE) that also includes an excellent benefits package and stock options
Job DescriptionGreat opportunity for an experienced
ASIC Physical Designer
to grow with an exciting fabless semiconductor company. The candidate is responsible for
Place and Route ,
Timing Closure
and
Physical Verification of large digital and high speed digital subsystems or chip top level.
The candidate must have a proven track record in leading the physical design effort of very large (>100M cells) high performance, low power, and high speed circuits (>500MHz). The ideal candidate will have an in depth understanding of the design process especially the Physical Design side, be comfortable floor planning from top down, and have extensive experience developing and using cutting edge physical design flows.
Required Skills and ExperienceThis is a
Senior-level position
that requires at least 10 years’ industry experience with the following:Proficient at using
Innovus (all phases), Tempus, Tempus TSO, QRC, VoltusHave led
chip top level Physical Design effort of large chips (>100M cells)or subsystemsExperience in setting up or using power estimation/IR drop flow using industry standard tools like Cadence VoltusExperience in
FinFet technologies (16nm and below)
including multi-Vt cell librariesAbility to work closely with design engineers and take feedback. Some of the blocks contain in-house or external large analog circuitsCalibre DRC/LVS, fill, DFM, PERC (ESD)Scripting ability (TCL, PERL, Python, Skill)Understanding of DFM and electromigration concerns forExperience with advanced clock trees, skew management, and clock domain crossingExperience with cloning and pipelining for timing closure
If interested in learning more about this position, please email your resume to
sgephart@geologics.com
and I will follow up with more information.
Thanks,
Sam GephartRecruiterGeoLogics Corporation888-303-3603sgephart@geologics.comhttps://www.linkedin.com/in/sam-gephart/
GeoLogics
is working with a hiring manager at
an innovative Fabless Semiconductor Company
and he is in search of
2
Senior ASIC Physical Design Lead , needed for a hybrid-salaried position.
2 Senior ASIC Physical Design LeadMust be a United States Citizen or Green Card HolderHybrid Position – Orange County/San Diego (3 day’s on/2 day’s off)888-303-3603
Salaried position (DOE) that also includes an excellent benefits package and stock options
Job DescriptionGreat opportunity for an experienced
ASIC Physical Designer
to grow with an exciting fabless semiconductor company. The candidate is responsible for
Place and Route ,
Timing Closure
and
Physical Verification of large digital and high speed digital subsystems or chip top level.
The candidate must have a proven track record in leading the physical design effort of very large (>100M cells) high performance, low power, and high speed circuits (>500MHz). The ideal candidate will have an in depth understanding of the design process especially the Physical Design side, be comfortable floor planning from top down, and have extensive experience developing and using cutting edge physical design flows.
Required Skills and ExperienceThis is a
Senior-level position
that requires at least 10 years’ industry experience with the following:Proficient at using
Innovus (all phases), Tempus, Tempus TSO, QRC, VoltusHave led
chip top level Physical Design effort of large chips (>100M cells)or subsystemsExperience in setting up or using power estimation/IR drop flow using industry standard tools like Cadence VoltusExperience in
FinFet technologies (16nm and below)
including multi-Vt cell librariesAbility to work closely with design engineers and take feedback. Some of the blocks contain in-house or external large analog circuitsCalibre DRC/LVS, fill, DFM, PERC (ESD)Scripting ability (TCL, PERL, Python, Skill)Understanding of DFM and electromigration concerns forExperience with advanced clock trees, skew management, and clock domain crossingExperience with cloning and pipelining for timing closure
If interested in learning more about this position, please email your resume to
sgephart@geologics.com
and I will follow up with more information.
Thanks,
Sam GephartRecruiterGeoLogics Corporation888-303-3603sgephart@geologics.comhttps://www.linkedin.com/in/sam-gephart/