NXP Semiconductors
Back End Design Methodology Lead
NXP Semiconductors, San Diego, California, United States, 92189
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Back End Design Methodology Lead
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locations
San Diego (Treena St)
Austin (Oakhill, Office)
time type
Full time
posted on
Posted 2 Days Ago
job requisition id
R-10053976
Directs and guides the activities of a team with prime responsibility in Design Methodologies and Tools. Evaluates final results of research and development projects to assure accomplishment of technical objectives. Reviews progress of technical projects and makes recommendations for actions necessary to achieve desired results. Selects, develops, and evaluates personnel to ensure the efficient operation of the function.Responsibilities include:Drive frontend and backend implementation methodology from RTL to gds2, including synthesis, FV, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementationInterface and drive EDA vendors to meet requirementsInterface with key stakeholders from design, implementation, and management to gather requirements and define roadmap and strategy for backend methodologyHands-on physical implementation and timing closure of core platforms and SoC'sWork with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pinStreamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation ) and develop/enhance auto ECO generation scripts for timing closureFloor planning , physical synthesis and physical design closure of large complex designs at 1GHz+ clock cyclesSynthesis flow and methodology for a low-power SoCDrive physical design and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster level, and/or full chip levelQualifications:BS/MS in EE/CS with 15+ years of hands-on experience on design implementation, CAD software or flow development on high-performance IPs and/or SOC designs.Proven track records of leading/architecting flow/tool development.Demonstrated design and methodology expertise on building ASIC chips in 5nm and below process nodes.Experience working and leading teams across multiple geos is a MUST.Demonstrated experience in building CAD flows that focus on improving designer productivity and quality including all available technologies.Demonstrated understanding of all aspects of ASIC design flows, SoC integration, Low power, Functional safety, DFT, and ATPG flows. This understanding is essential for you to drive methodology unification across a diverse set of business units and SOCs.Solid knowledge of chip integration and chip signoff. This knowledge will be essential for you to design tools, flows and methodologies for designing chips/chiplets/IPs that would all work seamlessly with each other.Experience working, collaborating and driving EDA vendors to meet requirements, expectations and deliverable schedulesThe base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:$197,000 to $270,800 annually More information about NXP in the United States...NXP is an Equal
Opportunity/Affirmative
Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.Similar Jobs (3)
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Posted 30+ Days AgoNXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.comBright Minds. Bright Futures.
We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.Commitment At NXP.
We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality .Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips .
#J-18808-Ljbffr
Back End Design Methodology Lead
Apply
locations
San Diego (Treena St)
Austin (Oakhill, Office)
time type
Full time
posted on
Posted 2 Days Ago
job requisition id
R-10053976
Directs and guides the activities of a team with prime responsibility in Design Methodologies and Tools. Evaluates final results of research and development projects to assure accomplishment of technical objectives. Reviews progress of technical projects and makes recommendations for actions necessary to achieve desired results. Selects, develops, and evaluates personnel to ensure the efficient operation of the function.Responsibilities include:Drive frontend and backend implementation methodology from RTL to gds2, including synthesis, FV, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementationInterface and drive EDA vendors to meet requirementsInterface with key stakeholders from design, implementation, and management to gather requirements and define roadmap and strategy for backend methodologyHands-on physical implementation and timing closure of core platforms and SoC'sWork with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pinStreamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation ) and develop/enhance auto ECO generation scripts for timing closureFloor planning , physical synthesis and physical design closure of large complex designs at 1GHz+ clock cyclesSynthesis flow and methodology for a low-power SoCDrive physical design and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster level, and/or full chip levelQualifications:BS/MS in EE/CS with 15+ years of hands-on experience on design implementation, CAD software or flow development on high-performance IPs and/or SOC designs.Proven track records of leading/architecting flow/tool development.Demonstrated design and methodology expertise on building ASIC chips in 5nm and below process nodes.Experience working and leading teams across multiple geos is a MUST.Demonstrated experience in building CAD flows that focus on improving designer productivity and quality including all available technologies.Demonstrated understanding of all aspects of ASIC design flows, SoC integration, Low power, Functional safety, DFT, and ATPG flows. This understanding is essential for you to drive methodology unification across a diverse set of business units and SOCs.Solid knowledge of chip integration and chip signoff. This knowledge will be essential for you to design tools, flows and methodologies for designing chips/chiplets/IPs that would all work seamlessly with each other.Experience working, collaborating and driving EDA vendors to meet requirements, expectations and deliverable schedulesThe base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:$197,000 to $270,800 annually More information about NXP in the United States...NXP is an Equal
Opportunity/Affirmative
Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.Similar Jobs (3)
AI/ML driven ASIC Design and Implementation Automation Lead
locations
San Diego (Treena St)
time type
Full time
posted on
Posted 30+ Days Ago
ASIC Design and Implementation Automation Lead
locations
San Diego (Treena St)
time type
Full time
posted on
Posted 30 Days Ago
Director, IP Design Engineering
locations
2 Locations
time type
Full time
posted on
Posted 30+ Days AgoNXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.comBright Minds. Bright Futures.
We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.Commitment At NXP.
We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality .Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips .
#J-18808-Ljbffr