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Design Engr - Verification II
The Fountain Group - Austin, Texas, us, 78716 9 days ago
Hello,My name is Ram, and I am a Recruiter with The Fountain Group. We are a national staffing firm and are currently seeking aVerification Design Eng...
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CPU Design Technology Specialist
BCG Attorney Search - Los Angeles, California, United States, 90079 1 days ago
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FalconSmartIT - Seattle, Washington, us, 98127 3 days ago
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MIPS Technologies - Dallas, Texas, United States, 75215 1 months ago
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Mixed Signal IC Design Lead
HRL Laboratories - Calabasas, California, United States, 91302 4 days ago
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Senior ISP RTL Design Manager
OMNIVISION - Iselin, New Jersey, us, 08830 23 days ago
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Go to next pageThe Fountain Group - Austin, Texas, us, 78716
Work at The Fountain Group
Hello,
My name is Ram, and I am a Recruiter with The Fountain Group. We are a national staffing firm and are currently seeking a
Verification Design Engineer
for a prominent client of ours. This position is located in
Austin, TX
If you are interested in hearing more about the position, please respond to this posting with your resume attached or contact me at 813-444-5839 / ram.n@thefountaingroup.com.
Please forward this email to any friends or colleagues as we do offer a Referral Bonus for any candidate hired.
Job Title: Verification Design EngineerLocation: Austin, TX (Remote/Hybrid)Duration: 12 months contract
Job Description:Requirements and responsibilities
Responsible for the successful verification of non-volatile memory modules from RTL development through final releases.Working closely with design engineering and verification teams to resolve failure issues and align priorities to achieve on-time delivery.Determine applicability of tools for project success.Ensure verification coverage, regression metrics and appropriate reviews are met before each delivery.Skills and knowledge:
7+ years of experience with Functional VerificationStrong knowledge of Verilog/System VerilogExperience with UVM is a must.Knowledge of C/C++RTL debugging experience.
See details and apply
Design Engr - Verification II