Coherent Interconnect Microarchitecture & Logic Design - Full Tim...
Rivos - Santa Clara, California, us, 95053![Rivos](/api/image?src=https%3A%2F%2Fgeneral-board-default.s3.us-east-2.amazonaws.com%2Fpublic%2Fimages%2Fdesk-360x180.webp&w=640&q=75&f=webp)
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Overview
ResponsibilitiesMicroarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
RequirementsThorough knowledge of large scale on-chip coherent or non-coherent interconnect/fabric architectureKnowledge of one or more on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink, APB or similar protocolsKnowledge of cache coherent memory systems and interconnectKnowledge of system caches and directory snoop filter protocolsFamiliarity with different on-chip network topologies: mesh, ring, crossbar, etcUnderstanding of high performance and low power microarchitecture techniques and trade-offsProficiency in SystemVerilog or Verilog RTL codingKnowledge of logic design principles along with timing and power implicationsExperience with simulators and waveform debugging tools
Education and ExperiencePhD, Master's Degree or Bachelor's Degree in technical subject area.