Tbwa Chiat/Day Inc
Principal SoC Physical Design Consultant Irvine or San Diego
Tbwa Chiat/Day Inc - California, Missouri, United States, 65018
Work at Tbwa Chiat/Day Inc
Overview
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Overview
InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.
The information below covers the role requirements, expected candidate experience, and accompanying qualifications. Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation. As a SoC Physical Design Consultant, you will contribute to physical design in developing novel/game-changing cellular infrastructure radio and ASIC solutions. You will provide solutions' features, architectures, device functional specifications, and technical guidance on block physical implementation to a multi-site team of engineers. This contract position is in Irvine, CA or San Diego, CA, but remote is possible. Key Responsibilities: Drive chip level integration of digital and analog IPs and provide technical direction. Contribute to all aspects of ASIC integration effort including floor planning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. Perform block-level implementation using place and route techniques to meet area/timing and power requirements when needed. Drive clock tree planning and implementation to achieve the best energy, performance, and area goals. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Work directly with the Synthesis/Timing Team to ensure Design closure. Manage quality deliverables and execute excellent physical designs in a timely manner. Job Qualifications: MS in Electrical Engineering plus 15 or more years of experience in ASIC physical design. Significant experience in chip assembly process of large SOCs in advanced process nodes. Able to contribute as an individual contributor on block level physical implementation, P&R. Deep understanding of Physical Design, Integration, STA, and Physical Verification. Expert in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification. Hands-on experience in block-level floor-planning, power planning, placement, clock tree synthesis, routing, LVS/DRC/ERC, timing closure, signoff, and engineering change orders (ECO's). Knowledge and skills in optimizing PPA through floor-planning, placement and timing constraints, useful skew, and similar techniques. Experience with the Cadence digital EDA toolset (Innovus / Quantus / Tempus / Conformal). Ability to use scripting languages to automate process flow. Team player with good interpersonal and communication skills. Experience with DFT flow. Ability to be proactive and have a strategic mindset in addition to having tactical problem-solving experience. Familiarity with industry-standard interfaces.
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The information below covers the role requirements, expected candidate experience, and accompanying qualifications. Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation. As a SoC Physical Design Consultant, you will contribute to physical design in developing novel/game-changing cellular infrastructure radio and ASIC solutions. You will provide solutions' features, architectures, device functional specifications, and technical guidance on block physical implementation to a multi-site team of engineers. This contract position is in Irvine, CA or San Diego, CA, but remote is possible. Key Responsibilities: Drive chip level integration of digital and analog IPs and provide technical direction. Contribute to all aspects of ASIC integration effort including floor planning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. Perform block-level implementation using place and route techniques to meet area/timing and power requirements when needed. Drive clock tree planning and implementation to achieve the best energy, performance, and area goals. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Work directly with the Synthesis/Timing Team to ensure Design closure. Manage quality deliverables and execute excellent physical designs in a timely manner. Job Qualifications: MS in Electrical Engineering plus 15 or more years of experience in ASIC physical design. Significant experience in chip assembly process of large SOCs in advanced process nodes. Able to contribute as an individual contributor on block level physical implementation, P&R. Deep understanding of Physical Design, Integration, STA, and Physical Verification. Expert in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification. Hands-on experience in block-level floor-planning, power planning, placement, clock tree synthesis, routing, LVS/DRC/ERC, timing closure, signoff, and engineering change orders (ECO's). Knowledge and skills in optimizing PPA through floor-planning, placement and timing constraints, useful skew, and similar techniques. Experience with the Cadence digital EDA toolset (Innovus / Quantus / Tempus / Conformal). Ability to use scripting languages to automate process flow. Team player with good interpersonal and communication skills. Experience with DFT flow. Ability to be proactive and have a strategic mindset in addition to having tactical problem-solving experience. Familiarity with industry-standard interfaces.
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