Synopsys Inc
Senior SOC Design Manager
Synopsys Inc - Sunnyvale, California, United States, 94087
Work at Synopsys Inc
Overview
- View job
Overview
Join to apply for the
Senior SOC Design Manager
role at
Synopsys Inc .
Is your CV ready If so, and you are confident this is the role for you, make sure to apply asap. We are seeking a seasoned design engineer with over 12 years of experience in ASIC/FPGA design and verification, who is passionate about leading teams and driving complex projects to successful completion. Role Overview This role involves managing and leading a team of SoC/Subsystem Design Engineers, collaborating with customers to understand their needs, and applying modern design processes for ASIC designs. You will be responsible for guiding the design from requirements to implementation, including microarchitecture, RTL development, verification, and timing closure. Responsibilities
Manage and mentor a team of design engineers for various customer projects. Work closely with clients to define design scope and activities. Lead design and review of System Verilog RTL code for complex designs. Implement industry-standard design methodologies for clocking, resets, and control/data paths. Qualifications
Bachelor’s or Master’s Degree in Electrical or Computer Engineering. Proficiency in System Verilog RTL coding and review. Experience with vendor tools in ASIC development (Simulators, Synthesis, STA, etc.). Knowledge of protocols such as PCIe, Ethernet, UCIe. Ideal Candidate Attributes Collaborative, innovative, with excellent communication skills, strategic thinking, and problem-solving abilities. Capable of working independently and tackling significant challenges. Additional Information This position is full-time, at a mid-senior level, within the Design, Consulting, and Engineering functions, in the Semiconductor Manufacturing, Software Development, and Computer Hardware industries.
#J-18808-Ljbffr
Senior SOC Design Manager
role at
Synopsys Inc .
Is your CV ready If so, and you are confident this is the role for you, make sure to apply asap. We are seeking a seasoned design engineer with over 12 years of experience in ASIC/FPGA design and verification, who is passionate about leading teams and driving complex projects to successful completion. Role Overview This role involves managing and leading a team of SoC/Subsystem Design Engineers, collaborating with customers to understand their needs, and applying modern design processes for ASIC designs. You will be responsible for guiding the design from requirements to implementation, including microarchitecture, RTL development, verification, and timing closure. Responsibilities
Manage and mentor a team of design engineers for various customer projects. Work closely with clients to define design scope and activities. Lead design and review of System Verilog RTL code for complex designs. Implement industry-standard design methodologies for clocking, resets, and control/data paths. Qualifications
Bachelor’s or Master’s Degree in Electrical or Computer Engineering. Proficiency in System Verilog RTL coding and review. Experience with vendor tools in ASIC development (Simulators, Synthesis, STA, etc.). Knowledge of protocols such as PCIe, Ethernet, UCIe. Ideal Candidate Attributes Collaborative, innovative, with excellent communication skills, strategic thinking, and problem-solving abilities. Capable of working independently and tackling significant challenges. Additional Information This position is full-time, at a mid-senior level, within the Design, Consulting, and Engineering functions, in the Semiconductor Manufacturing, Software Development, and Computer Hardware industries.
#J-18808-Ljbffr