Senior Physical Designer
Blackrock Neurotech LLC - Salt Lake City, Utah, United States, 84106![Blackrock Neurotech LLC](/api/image?src=https%3A%2F%2Fgeneral-board-default.s3.us-east-2.amazonaws.com%2Fpublic%2Fimages%2Fdesk-360x180.webp&w=640&q=75&f=webp)
Work at Blackrock Neurotech LLC
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Overview
Senior Physical Designer
Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below.Department:
BCIJob Reports To:
Head of BCILocation:
Salt Lake City or RemotePOSITION OVERVIEW:The Physical Designer engineer will work on novel state of the art BCI systems featuring custom ASICs. The Physical Designer engineer will support the design of the ASIC and will collaborate with the ASIC AMS designers/manufacturing teams/ and system level engineers during R&D to ensure successful tapeouts.QUALIFICATION REQUIREMENTSPhD in electrical engineering or computer engineering.Minimum 5 years of experience in physical design and ASIC design.IDEAL COMPETENCIES
Siemens/Synopsys/Cadence tools.Strong scripting skill with languages like TCL, Perl, or Python for automation tasks.Knowledge in ASIC design flow from spec to test and validation.Knowledge in complex SoC and active interposer assembly.Knowledge in medical devices.ESSENTIAL JOB DUTIES
The Physical Design Engineer is responsible for integrating analog and mixed signal IPs, as well as high-speed interfaces, into subsystems or AMS components. They collaborate with package and platform teams to ensure seamless AMS integration.They support pathfinding studies during silicon development and provide feedback to the silicon and packaging teams regarding AMS integration and tradeoffs. The engineer guides the integration process from specification documentation to silicon tapeout and offers debugging support for analog functionality-related issues in the product.Their expertise lies in PnR and design verification flows, understanding packaging effects, and managing integration challenges in AMS designs to achieve optimal overall circuit performance.They closely collaborate with analog IP, SoC architecture, SoC design, package, and platform design functions to meet the analog specification requirements for the product.
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