Summer Intern, Design Verification
Cirrus Logic - Chandler, Arizona, United States, 85249![Cirrus Logic](/api/image?src=https%3A%2F%2Fgeneral-board-default.s3.us-east-2.amazonaws.com%2Fpublic%2Fimages%2Fdesk-360x180.webp&w=640&q=75&f=webp)
Work at Cirrus Logic
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Overview
Assist with verification planning.Support with testbench developmentMaintenance with failure analysis and resolutionHelp with coverage analysis and populationWork on digital/mixed-signal modeling, directed/constraint-random test generation, and flow developmentREQUIRED KNOWLEDGE, SKILLS AND EXPERIENCE:
Must have a BSEE/BSCE and be pursuing an MSEE/MSCEStrong background with Verilog / SystemVerilogPREFERRED KNOWLEDGE, SKILLS AND EXPERIENCE
Experience with UVMScripting (e.g. Perl, Python, Unix/Linux shell)Knowledge of signal processing concepts, MatlabObject oriented programming (e.g. SystemVerilog)This internship is on-site. This opportunity is available for the
summer semester only . It is available only to students currently enrolled in a MS or PhD program in Electrical Engineering maintaining a GPA of 3.6 or above, and who will be returning to school for at least one semester following completion of his/her internship. Candidate must be available for full-time employment during the internship.Diversity drives innovation at Cirrus Logic. Different approaches, ideas and points of view are both valued and respected, and employees are rewarded for their skills, experience and performance. Additionally, Cirrus Logic is an Equal Opportunity/Affirmative Action Employer, and we do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.